[XS] Change in coreboot[main]: soc/intel/alderlake/romstage: Update UFS disable sequence

[Subrata Banik (Code Review)]

Attention is currently required from: Dinesh Gehlot, Intel coreboot Reviewers, Jayvik Desai, Kapil Porwal, Karthik Ramasubramanian, Nick Vaccaro.

Subrata Banik has posted comments on this change by Karthik Ramasubramanian. ( https://review.coreboot.org/c/coreboot/+/86170?usp=email )

Change subject: soc/intel/alderlake/romstage: Update UFS disable sequence
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Patch Set 3:

(1 comment)

File src/soc/intel/alderlake/romstage/romstage.c:

https://review.coreboot.org/c/coreboot/+/86170/comment/80c00937_ed750faa?usp... :
PS3, Line 202: 		if ((ps->prev_sleep_state == ACPI_S5 ||
             : 		     cse_match_current_pm_event(PWR_CYCLE_RESET_CMOFF)) &&
             : 		    !mainboard_expects_another_reset()) {
with this CL, do we still need CB:86111 ?

I believe we can avoid sending side band communication in all other boots like S0 cycles ? the code logic in 202-204 is enough to enforce disabling UFS and issue a warm reboot.