Change in coreboot[master]: soc/amd/cezanne/fch: disable 48MHz output in S0i3 - coreboot-gerrit

20 Dec 2021


      Attention is currently required from: Marshall Dawson, Felix Held.
Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60125 )
Change subject: soc/amd/cezanne/fch: disable 48MHz output in S0i3
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Patch Set 2: Code-Review+2
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: If445f5825dc7b795c95d73c061156cc485421ada
Gerrit-Change-Number: 60125
Gerrit-PatchSet: 2
Gerrit-Owner: Felix Held felix-coreboot@felixheld.de
Gerrit-Reviewer: Jason Glenesk jason.glenesk@gmail.com
Gerrit-Reviewer: Marshall Dawson marshalldawson3rd@gmail.com
Gerrit-Reviewer: Paul Menzel paulepanter@mailbox.org
Gerrit-Reviewer: Raul Rangel rrangel@chromium.org
Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org
Gerrit-Attention: Marshall Dawson marshalldawson3rd@gmail.com
Gerrit-Attention: Felix Held felix-coreboot@felixheld.de
Gerrit-Comment-Date: Mon, 20 Dec 2021 15:58:52 +0000
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