Change in coreboot[master]: soc/intel/skylake: Drop always-zero ProbelessTrace dt setting
Hello Felix Singer, V Sowmya, Nico Huber, Furquan Shaikh, Tim Wawrzynczak, Subrata Banik, Arthur Heymans, Michael Niewöhner, Patrick Rudolph,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/48576
to review the following change.
Change subject: soc/intel/skylake: Drop always-zero ProbelessTrace dt setting ......................................................................
soc/intel/skylake: Drop always-zero ProbelessTrace dt setting
This seems to be a debugging option. Since unset devicetree options default to zero, drop the setting. If it is needed in the future, a user-visible Kconfig option would probably make more sense.
Change-Id: I0a71bc407fa92da3dcc0e3dbd666438d4280ffcb Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/mainboard/51nb/x210/devicetree.cb M src/mainboard/google/eve/devicetree.cb M src/mainboard/google/fizz/variants/baseboard/devicetree.cb M src/mainboard/google/glados/devicetree.cb M src/mainboard/google/poppy/variants/atlas/devicetree.cb M src/mainboard/google/poppy/variants/baseboard/devicetree.cb M src/mainboard/google/poppy/variants/nami/devicetree.cb M src/mainboard/google/poppy/variants/nautilus/devicetree.cb M src/mainboard/google/poppy/variants/nocturne/devicetree.cb M src/mainboard/google/poppy/variants/rammus/devicetree.cb M src/mainboard/google/poppy/variants/soraka/devicetree.cb M src/mainboard/libretrend/lt1000/devicetree.cb M src/mainboard/protectli/vault_kbl/devicetree.cb M src/mainboard/purism/librem_skl/devicetree.cb M src/mainboard/razer/blade_stealth_kbl/devicetree.cb M src/soc/intel/skylake/chip.h M src/soc/intel/skylake/romstage/romstage.c 17 files changed, 1 insertion(+), 19 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/48576/1
diff --git a/src/mainboard/51nb/x210/devicetree.cb b/src/mainboard/51nb/x210/devicetree.cb index 0e408f8..43f272e 100644 --- a/src/mainboard/51nb/x210/devicetree.cb +++ b/src/mainboard/51nb/x210/devicetree.cb @@ -32,7 +32,6 @@ register "dptf_enable" = "0"
# FSP Configuration - register "ProbelessTrace" = "0" register "SataSalpSupport" = "1" register "SataMode" = "0"
diff --git a/src/mainboard/google/eve/devicetree.cb b/src/mainboard/google/eve/devicetree.cb index f8a92d8..0e76de1 100644 --- a/src/mainboard/google/eve/devicetree.cb +++ b/src/mainboard/google/eve/devicetree.cb @@ -35,7 +35,6 @@ register "gen3_dec" = "0x00fc0901"
# FSP Configuration - register "ProbelessTrace" = "0" register "SataSalpSupport" = "0" register "SataMode" = "0" register "SataPortsEnable[0]" = "0" diff --git a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb index 430334a..8c31f9ac 100644 --- a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb @@ -64,7 +64,6 @@ register "s0ix_enable" = "1"
# FSP Configuration - register "ProbelessTrace" = "0" register "SataSalpSupport" = "0" register "SataMode" = "0" register "SataPortsEnable[0]" = "1" diff --git a/src/mainboard/google/glados/devicetree.cb b/src/mainboard/google/glados/devicetree.cb index 4f8beef..127334e 100644 --- a/src/mainboard/google/glados/devicetree.cb +++ b/src/mainboard/google/glados/devicetree.cb @@ -34,7 +34,6 @@ register "dptf_enable" = "1"
# FSP Configuration - register "ProbelessTrace" = "0" register "SataSalpSupport" = "0" register "SataMode" = "0" register "SataPortsEnable[0]" = "0" diff --git a/src/mainboard/google/poppy/variants/atlas/devicetree.cb b/src/mainboard/google/poppy/variants/atlas/devicetree.cb index 4fd71d5..a14e927 100644 --- a/src/mainboard/google/poppy/variants/atlas/devicetree.cb +++ b/src/mainboard/google/poppy/variants/atlas/devicetree.cb @@ -41,7 +41,6 @@ register "CmdTriStateDis" = "1"
# FSP Configuration - register "ProbelessTrace" = "0" register "SataSalpSupport" = "0" register "SataMode" = "0" register "SataPortsEnable[0]" = "0" diff --git a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb index 9383642..4bfac6d 100644 --- a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb @@ -31,7 +31,6 @@ register "s0ix_enable" = "1"
# FSP Configuration - register "ProbelessTrace" = "0" register "SataSalpSupport" = "0" register "SataMode" = "0" register "SataPortsEnable[0]" = "0" diff --git a/src/mainboard/google/poppy/variants/nami/devicetree.cb b/src/mainboard/google/poppy/variants/nami/devicetree.cb index 65ecc8f..25d720e 100644 --- a/src/mainboard/google/poppy/variants/nami/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nami/devicetree.cb @@ -31,7 +31,6 @@ register "s0ix_enable" = "1"
# FSP Configuration - register "ProbelessTrace" = "0" register "SataSalpSupport" = "0" register "SataMode" = "0" register "DspEnable" = "1" diff --git a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb index ec55645..9563298 100644 --- a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb @@ -31,7 +31,6 @@ register "s0ix_enable" = "1"
# FSP Configuration - register "ProbelessTrace" = "0" register "SataSalpSupport" = "0" register "SataMode" = "0" register "SataPortsEnable[0]" = "0" diff --git a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb index 6b58e0b..899990d 100644 --- a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb @@ -36,7 +36,6 @@ register "CmdTriStateDis" = "1"
# FSP Configuration - register "ProbelessTrace" = "0" register "SataSalpSupport" = "0" register "SataMode" = "0" register "SataPortsEnable[0]" = "0" diff --git a/src/mainboard/google/poppy/variants/rammus/devicetree.cb b/src/mainboard/google/poppy/variants/rammus/devicetree.cb index 8418231..ff117c8 100644 --- a/src/mainboard/google/poppy/variants/rammus/devicetree.cb +++ b/src/mainboard/google/poppy/variants/rammus/devicetree.cb @@ -41,7 +41,6 @@ register "CmdTriStateDis" = "1"
# FSP Configuration - register "ProbelessTrace" = "0" register "SataSalpSupport" = "0" register "SataMode" = "0" register "SataPortsEnable[0]" = "0" diff --git a/src/mainboard/google/poppy/variants/soraka/devicetree.cb b/src/mainboard/google/poppy/variants/soraka/devicetree.cb index 8e5caf3..6a37b8a 100644 --- a/src/mainboard/google/poppy/variants/soraka/devicetree.cb +++ b/src/mainboard/google/poppy/variants/soraka/devicetree.cb @@ -31,7 +31,6 @@ register "s0ix_enable" = "1"
# FSP Configuration - register "ProbelessTrace" = "0" register "SataSalpSupport" = "0" register "SataMode" = "0" register "SataPortsEnable[0]" = "0" diff --git a/src/mainboard/libretrend/lt1000/devicetree.cb b/src/mainboard/libretrend/lt1000/devicetree.cb index f6e73c6..9fedde5 100644 --- a/src/mainboard/libretrend/lt1000/devicetree.cb +++ b/src/mainboard/libretrend/lt1000/devicetree.cb @@ -34,7 +34,6 @@ register "dptf_enable" = "0"
# FSP Configuration - register "ProbelessTrace" = "0" register "SataSalpSupport" = "0" register "SataMode" = "0" register "SataPortsEnable[0]" = "1" diff --git a/src/mainboard/protectli/vault_kbl/devicetree.cb b/src/mainboard/protectli/vault_kbl/devicetree.cb index d8e68a2..abbfda4 100644 --- a/src/mainboard/protectli/vault_kbl/devicetree.cb +++ b/src/mainboard/protectli/vault_kbl/devicetree.cb @@ -31,7 +31,6 @@ register "tcc_offset" = "5" # TCC of 95C
# FSP Configuration - register "ProbelessTrace" = "0" register "SataSalpSupport" = "0" register "SataMode" = "0" register "DspEnable" = "0" diff --git a/src/mainboard/purism/librem_skl/devicetree.cb b/src/mainboard/purism/librem_skl/devicetree.cb index 6d98772..c59df40 100644 --- a/src/mainboard/purism/librem_skl/devicetree.cb +++ b/src/mainboard/purism/librem_skl/devicetree.cb @@ -41,7 +41,6 @@ register "dptf_enable" = "0"
# FSP Configuration - register "ProbelessTrace" = "0" register "SataSalpSupport" = "0" register "SataMode" = "0" register "SataPortsEnable[0]" = "1" diff --git a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb index 8f3e0d6..44b3523 100644 --- a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb +++ b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb @@ -23,7 +23,6 @@ register "dptf_enable" = "0"
# FSP Configuration - register "ProbelessTrace" = "0" register "SataSalpSupport" = "0" register "SataMode" = "0" register "SataPortsEnable[0]" = "0" diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index 8d93ac0..e738179 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -90,9 +90,6 @@ /* Whether to ignore VT-d support of the SKU */ int ignore_vtd;
- /* Probeless Trace function */ - u8 ProbelessTrace; - /* * System Agent dynamic frequency configuration * When enabled memory will be trained at two different frequencies. diff --git a/src/soc/intel/skylake/romstage/romstage.c b/src/soc/intel/skylake/romstage/romstage.c index 79fb464..c826187 100644 --- a/src/soc/intel/skylake/romstage/romstage.c +++ b/src/soc/intel/skylake/romstage/romstage.c @@ -216,7 +216,7 @@ m_cfg->MmioSize = 0x800; /* 2GB in MB */ m_cfg->TsegSize = CONFIG_SMM_TSEG_SIZE; m_cfg->IedSize = CONFIG_IED_REGION_SIZE; - m_cfg->ProbelessTrace = config->ProbelessTrace; + m_cfg->ProbelessTrace = 0; m_cfg->SaGv = config->SaGv; m_cfg->UserBd = BOARD_TYPE_ULT_ULX; m_cfg->RMT = config->Rmt;
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48576 )
Change subject: soc/intel/skylake: Drop always-zero ProbelessTrace dt setting ......................................................................
Patch Set 1: Code-Review+2
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48576 )
Change subject: soc/intel/skylake: Drop always-zero ProbelessTrace dt setting ......................................................................
Patch Set 2: Code-Review+1
(1 comment)
https://review.coreboot.org/c/coreboot/+/48576/2/src/soc/intel/skylake/romst... File src/soc/intel/skylake/romstage/romstage.c:
https://review.coreboot.org/c/coreboot/+/48576/2/src/soc/intel/skylake/romst... PS2, Line 219: m_cfg->ProbelessTrace = 0; fsp defaults to off (0) -> drop it
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48576 )
Change subject: soc/intel/skylake: Drop always-zero ProbelessTrace dt setting ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/48576/2/src/soc/intel/skylake/romst... File src/soc/intel/skylake/romstage/romstage.c:
https://review.coreboot.org/c/coreboot/+/48576/2/src/soc/intel/skylake/romst... PS2, Line 219: m_cfg->ProbelessTrace = 0;
fsp defaults to off (0) -> drop it
This patch is meant to preserve behavior. I've no idea of what happens if I don't set this value.
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48576 )
Change subject: soc/intel/skylake: Drop always-zero ProbelessTrace dt setting ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/48576/2/src/soc/intel/skylake/romst... File src/soc/intel/skylake/romstage/romstage.c:
https://review.coreboot.org/c/coreboot/+/48576/2/src/soc/intel/skylake/romst... PS2, Line 219: m_cfg->ProbelessTrace = 0;
This patch is meant to preserve behavior. I've no idea of what happens if I don't set this value.
not setting it preserves behaviour because fsp defaults to 0
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48576 )
Change subject: soc/intel/skylake: Drop always-zero ProbelessTrace dt setting ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/48576/2/src/soc/intel/skylake/romst... File src/soc/intel/skylake/romstage/romstage.c:
https://review.coreboot.org/c/coreboot/+/48576/2/src/soc/intel/skylake/romst... PS2, Line 219: m_cfg->ProbelessTrace = 0;
not setting it preserves behaviour because fsp defaults to 0
Done
Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/48576 )
Change subject: soc/intel/skylake: Drop always-zero ProbelessTrace dt setting ......................................................................
soc/intel/skylake: Drop always-zero ProbelessTrace dt setting
This seems to be a debugging option. Since unset devicetree options default to zero, drop the setting. If it is needed in the future, a user-visible Kconfig option would probably make more sense.
Change-Id: I0a71bc407fa92da3dcc0e3dbd666438d4280ffcb Signed-off-by: Angel Pons th3fanbus@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/48576 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Michael Niewöhner foss@mniewoehner.de Reviewed-by: Furquan Shaikh furquan@google.com --- M src/mainboard/51nb/x210/devicetree.cb M src/mainboard/google/eve/devicetree.cb M src/mainboard/google/fizz/variants/baseboard/devicetree.cb M src/mainboard/google/glados/devicetree.cb M src/mainboard/google/poppy/variants/atlas/devicetree.cb M src/mainboard/google/poppy/variants/baseboard/devicetree.cb M src/mainboard/google/poppy/variants/nami/devicetree.cb M src/mainboard/google/poppy/variants/nautilus/devicetree.cb M src/mainboard/google/poppy/variants/nocturne/devicetree.cb M src/mainboard/google/poppy/variants/rammus/devicetree.cb M src/mainboard/google/poppy/variants/soraka/devicetree.cb M src/mainboard/libretrend/lt1000/devicetree.cb M src/mainboard/protectli/vault_kbl/devicetree.cb M src/mainboard/purism/librem_skl/devicetree.cb M src/mainboard/razer/blade_stealth_kbl/devicetree.cb M src/soc/intel/skylake/chip.h M src/soc/intel/skylake/romstage/romstage.c 17 files changed, 1 insertion(+), 19 deletions(-)
Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved Michael Niewöhner: Looks good to me, but someone else must approve
diff --git a/src/mainboard/51nb/x210/devicetree.cb b/src/mainboard/51nb/x210/devicetree.cb index 0e408f8..43f272e 100644 --- a/src/mainboard/51nb/x210/devicetree.cb +++ b/src/mainboard/51nb/x210/devicetree.cb @@ -32,7 +32,6 @@ register "dptf_enable" = "0"
# FSP Configuration - register "ProbelessTrace" = "0" register "SataSalpSupport" = "1" register "SataMode" = "0"
diff --git a/src/mainboard/google/eve/devicetree.cb b/src/mainboard/google/eve/devicetree.cb index f8a92d8..0e76de1 100644 --- a/src/mainboard/google/eve/devicetree.cb +++ b/src/mainboard/google/eve/devicetree.cb @@ -35,7 +35,6 @@ register "gen3_dec" = "0x00fc0901"
# FSP Configuration - register "ProbelessTrace" = "0" register "SataSalpSupport" = "0" register "SataMode" = "0" register "SataPortsEnable[0]" = "0" diff --git a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb index 430334a..8c31f9ac 100644 --- a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb @@ -64,7 +64,6 @@ register "s0ix_enable" = "1"
# FSP Configuration - register "ProbelessTrace" = "0" register "SataSalpSupport" = "0" register "SataMode" = "0" register "SataPortsEnable[0]" = "1" diff --git a/src/mainboard/google/glados/devicetree.cb b/src/mainboard/google/glados/devicetree.cb index 4f8beef..127334e 100644 --- a/src/mainboard/google/glados/devicetree.cb +++ b/src/mainboard/google/glados/devicetree.cb @@ -34,7 +34,6 @@ register "dptf_enable" = "1"
# FSP Configuration - register "ProbelessTrace" = "0" register "SataSalpSupport" = "0" register "SataMode" = "0" register "SataPortsEnable[0]" = "0" diff --git a/src/mainboard/google/poppy/variants/atlas/devicetree.cb b/src/mainboard/google/poppy/variants/atlas/devicetree.cb index 4fd71d5..a14e927 100644 --- a/src/mainboard/google/poppy/variants/atlas/devicetree.cb +++ b/src/mainboard/google/poppy/variants/atlas/devicetree.cb @@ -41,7 +41,6 @@ register "CmdTriStateDis" = "1"
# FSP Configuration - register "ProbelessTrace" = "0" register "SataSalpSupport" = "0" register "SataMode" = "0" register "SataPortsEnable[0]" = "0" diff --git a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb index 9383642..4bfac6d 100644 --- a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb @@ -31,7 +31,6 @@ register "s0ix_enable" = "1"
# FSP Configuration - register "ProbelessTrace" = "0" register "SataSalpSupport" = "0" register "SataMode" = "0" register "SataPortsEnable[0]" = "0" diff --git a/src/mainboard/google/poppy/variants/nami/devicetree.cb b/src/mainboard/google/poppy/variants/nami/devicetree.cb index 65ecc8f..25d720e 100644 --- a/src/mainboard/google/poppy/variants/nami/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nami/devicetree.cb @@ -31,7 +31,6 @@ register "s0ix_enable" = "1"
# FSP Configuration - register "ProbelessTrace" = "0" register "SataSalpSupport" = "0" register "SataMode" = "0" register "DspEnable" = "1" diff --git a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb index ec55645..9563298 100644 --- a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb @@ -31,7 +31,6 @@ register "s0ix_enable" = "1"
# FSP Configuration - register "ProbelessTrace" = "0" register "SataSalpSupport" = "0" register "SataMode" = "0" register "SataPortsEnable[0]" = "0" diff --git a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb index 6b58e0b..899990d 100644 --- a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb @@ -36,7 +36,6 @@ register "CmdTriStateDis" = "1"
# FSP Configuration - register "ProbelessTrace" = "0" register "SataSalpSupport" = "0" register "SataMode" = "0" register "SataPortsEnable[0]" = "0" diff --git a/src/mainboard/google/poppy/variants/rammus/devicetree.cb b/src/mainboard/google/poppy/variants/rammus/devicetree.cb index 8418231..ff117c8 100644 --- a/src/mainboard/google/poppy/variants/rammus/devicetree.cb +++ b/src/mainboard/google/poppy/variants/rammus/devicetree.cb @@ -41,7 +41,6 @@ register "CmdTriStateDis" = "1"
# FSP Configuration - register "ProbelessTrace" = "0" register "SataSalpSupport" = "0" register "SataMode" = "0" register "SataPortsEnable[0]" = "0" diff --git a/src/mainboard/google/poppy/variants/soraka/devicetree.cb b/src/mainboard/google/poppy/variants/soraka/devicetree.cb index 8e5caf3..6a37b8a 100644 --- a/src/mainboard/google/poppy/variants/soraka/devicetree.cb +++ b/src/mainboard/google/poppy/variants/soraka/devicetree.cb @@ -31,7 +31,6 @@ register "s0ix_enable" = "1"
# FSP Configuration - register "ProbelessTrace" = "0" register "SataSalpSupport" = "0" register "SataMode" = "0" register "SataPortsEnable[0]" = "0" diff --git a/src/mainboard/libretrend/lt1000/devicetree.cb b/src/mainboard/libretrend/lt1000/devicetree.cb index f6e73c6..9fedde5 100644 --- a/src/mainboard/libretrend/lt1000/devicetree.cb +++ b/src/mainboard/libretrend/lt1000/devicetree.cb @@ -34,7 +34,6 @@ register "dptf_enable" = "0"
# FSP Configuration - register "ProbelessTrace" = "0" register "SataSalpSupport" = "0" register "SataMode" = "0" register "SataPortsEnable[0]" = "1" diff --git a/src/mainboard/protectli/vault_kbl/devicetree.cb b/src/mainboard/protectli/vault_kbl/devicetree.cb index d8e68a2..abbfda4 100644 --- a/src/mainboard/protectli/vault_kbl/devicetree.cb +++ b/src/mainboard/protectli/vault_kbl/devicetree.cb @@ -31,7 +31,6 @@ register "tcc_offset" = "5" # TCC of 95C
# FSP Configuration - register "ProbelessTrace" = "0" register "SataSalpSupport" = "0" register "SataMode" = "0" register "DspEnable" = "0" diff --git a/src/mainboard/purism/librem_skl/devicetree.cb b/src/mainboard/purism/librem_skl/devicetree.cb index 6d98772..c59df40 100644 --- a/src/mainboard/purism/librem_skl/devicetree.cb +++ b/src/mainboard/purism/librem_skl/devicetree.cb @@ -41,7 +41,6 @@ register "dptf_enable" = "0"
# FSP Configuration - register "ProbelessTrace" = "0" register "SataSalpSupport" = "0" register "SataMode" = "0" register "SataPortsEnable[0]" = "1" diff --git a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb index 8f3e0d6..44b3523 100644 --- a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb +++ b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb @@ -23,7 +23,6 @@ register "dptf_enable" = "0"
# FSP Configuration - register "ProbelessTrace" = "0" register "SataSalpSupport" = "0" register "SataMode" = "0" register "SataPortsEnable[0]" = "0" diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index 4d92410..f4744c9 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -90,9 +90,6 @@ /* Whether to ignore VT-d support of the SKU */ int ignore_vtd;
- /* Probeless Trace function */ - u8 ProbelessTrace; - /* * System Agent dynamic frequency configuration * When enabled memory will be trained at two different frequencies. diff --git a/src/soc/intel/skylake/romstage/romstage.c b/src/soc/intel/skylake/romstage/romstage.c index 79fb464..c826187 100644 --- a/src/soc/intel/skylake/romstage/romstage.c +++ b/src/soc/intel/skylake/romstage/romstage.c @@ -216,7 +216,7 @@ m_cfg->MmioSize = 0x800; /* 2GB in MB */ m_cfg->TsegSize = CONFIG_SMM_TSEG_SIZE; m_cfg->IedSize = CONFIG_IED_REGION_SIZE; - m_cfg->ProbelessTrace = config->ProbelessTrace; + m_cfg->ProbelessTrace = 0; m_cfg->SaGv = config->SaGv; m_cfg->UserBd = BOARD_TYPE_ULT_ULX; m_cfg->RMT = config->Rmt;
-
Angel Pons (Code Review) -
Furquan Shaikh (Code Review)
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Michael Niewöhner (Code Review)