Change in coreboot[master]: soc/intel/dnv: Fix ACPI reporting of root port interrupt routing

[Stephen Douthit (Code Review)]

Stephen Douthit has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34712 )

Change subject: soc/intel/dnv: Fix ACPI reporting of root port interrupt routing
......................................................................

soc/intel/dnv: Fix ACPI reporting of root port interrupt routing

pcie_port.asl defines an IRQM method that looks up legacy interrupt
swizzling based on incoming interrupt "pin" A-D and root port number.

Unfortunately the 8-bit root port number stored at offset 0x4F in the
config space matches the device number, not the 1-8 scheme used in
the LUT reported to the OS.

Fix the case values to match the hardware.

Change-Id: I103d632a4bc99461f02e05aa0f9a9eb7376770d9
Signed-off-by: Stephen Douthit 
---
M src/soc/intel/denverton_ns/acpi/pcie.asl
1 file changed, 8 insertions(+), 8 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/34712/1

diff --git a/src/soc/intel/denverton_ns/acpi/pcie.asl b/src/soc/intel/denverton_ns/acpi/pcie.asl
index cb14cf8..c9bbd3f 100644
--- a/src/soc/intel/denverton_ns/acpi/pcie.asl
+++ b/src/soc/intel/denverton_ns/acpi/pcie.asl
@@ -120,7 +120,7 @@

Switch (ToInteger (Arg0)) {
    	/* PCIe Root Port 1 */
-		Case (Package() { 1 }) {
+		Case (Package() { 9 }) {
    		If (PICM) {
    			Return (IQAA)
    		} Else {
@@ -129,7 +129,7 @@
    	}

/* PCIe Root Port 2 */
-		Case (Package() { 2 }) {
+		Case (Package() { 10 }) {
    		If (PICM) {
    			Return (IQBA)
    		} Else {
@@ -138,7 +138,7 @@
    	}

/* PCIe Root Port 3 */
-		Case (Package() { 3 }) {
+		Case (Package() { 11 }) {
    		If (PICM) {
    			Return (IQCA)
    		} Else {
@@ -147,7 +147,7 @@
    	}

/* PCIe Root Port 4 */
-		Case (Package() { 4 }) {
+		Case (Package() { 12 }) {
    		If (PICM) {
    			Return (IQDA)
    		} Else {
@@ -156,7 +156,7 @@
    	}

/* PCIe Root Port 5 */
-		Case (Package() { 5 }) {
+		Case (Package() { 14 }) {
    		If (PICM) {
    			Return (IQEA)
    		} Else {
@@ -165,7 +165,7 @@
    	}

/* PCIe Root Port 6 */
-		Case (Package() { 6 }) {
+		Case (Package() { 15 }) {
    		If (PICM) {
    			Return (IQFA)
    		} Else {
@@ -174,7 +174,7 @@
    	}

/* PCIe Root Port 7 */
-		Case (Package() { 7 }) {
+		Case (Package() { 16 }) {
    		If (PICM) {
    			Return (IQGA)
    		} Else {
@@ -183,7 +183,7 @@
    	}

/* PCIe Root Port 8 */
-		Case (Package() { 8 }) {
+		Case (Package() { 17 }) {
    		If (PICM) {
    			Return (IQHA)
    		} Else {

[Patrick Georgi (Code Review)]

Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34712 )

Change subject: soc/intel/dnv: Fix ACPI reporting of root port interrupt routing
......................................................................

Patch Set 1: Code-Review+2

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/34712 )

Change subject: soc/intel/dnv: Fix ACPI reporting of root port interrupt routing
......................................................................

soc/intel/dnv: Fix ACPI reporting of root port interrupt routing

pcie_port.asl defines an IRQM method that looks up legacy interrupt
swizzling based on incoming interrupt "pin" A-D and root port number.

Unfortunately the 8-bit root port number stored at offset 0x4F in the
config space matches the device number, not the 1-8 scheme used in
the LUT reported to the OS.

Fix the case values to match the hardware.

Change-Id: I103d632a4bc99461f02e05aa0f9a9eb7376770d9
Signed-off-by: Stephen Douthit 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34712
Tested-by: build bot (Jenkins) 
Reviewed-by: Patrick Georgi 
---
M src/soc/intel/denverton_ns/acpi/pcie.asl
1 file changed, 8 insertions(+), 8 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Patrick Georgi: Looks good to me, approved

diff --git a/src/soc/intel/denverton_ns/acpi/pcie.asl b/src/soc/intel/denverton_ns/acpi/pcie.asl
index cb14cf8..c9bbd3f 100644
--- a/src/soc/intel/denverton_ns/acpi/pcie.asl
+++ b/src/soc/intel/denverton_ns/acpi/pcie.asl
@@ -120,7 +120,7 @@

Switch (ToInteger (Arg0)) {
    	/* PCIe Root Port 1 */
-		Case (Package() { 1 }) {
+		Case (Package() { 9 }) {
    		If (PICM) {
    			Return (IQAA)
    		} Else {
@@ -129,7 +129,7 @@
    	}

/* PCIe Root Port 2 */
-		Case (Package() { 2 }) {
+		Case (Package() { 10 }) {
    		If (PICM) {
    			Return (IQBA)
    		} Else {
@@ -138,7 +138,7 @@
    	}

/* PCIe Root Port 3 */
-		Case (Package() { 3 }) {
+		Case (Package() { 11 }) {
    		If (PICM) {
    			Return (IQCA)
    		} Else {
@@ -147,7 +147,7 @@
    	}

/* PCIe Root Port 4 */
-		Case (Package() { 4 }) {
+		Case (Package() { 12 }) {
    		If (PICM) {
    			Return (IQDA)
    		} Else {
@@ -156,7 +156,7 @@
    	}

/* PCIe Root Port 5 */
-		Case (Package() { 5 }) {
+		Case (Package() { 14 }) {
    		If (PICM) {
    			Return (IQEA)
    		} Else {
@@ -165,7 +165,7 @@
    	}

/* PCIe Root Port 6 */
-		Case (Package() { 6 }) {
+		Case (Package() { 15 }) {
    		If (PICM) {
    			Return (IQFA)
    		} Else {
@@ -174,7 +174,7 @@
    	}

/* PCIe Root Port 7 */
-		Case (Package() { 7 }) {
+		Case (Package() { 16 }) {
    		If (PICM) {
    			Return (IQGA)
    		} Else {
@@ -183,7 +183,7 @@
    	}

/* PCIe Root Port 8 */
-		Case (Package() { 8 }) {
+		Case (Package() { 17 }) {
    		If (PICM) {
    			Return (IQHA)
    		} Else {