John Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32744
Change subject: soc/intel: Geminilake Refresh feature request support ......................................................................
soc/intel: Geminilake Refresh feature request support
Add 0x706a8 for GLK Refresh CPU stepping ID.
BUG=b:132414963 BRANCH=None TEST=Image built successfully.
Signed-off-by: John Zhao john.zhao@intel.com Change-Id: I4641d9bd4c82211e7200f617cae9043b0f2f38d1 --- M src/soc/intel/apollolake/cpu.c M src/soc/intel/common/block/cpu/mp_init.c M src/soc/intel/common/block/include/intelblocks/mp_init.h 3 files changed, 3 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/32744/1
diff --git a/src/soc/intel/apollolake/cpu.c b/src/soc/intel/apollolake/cpu.c index 11d15e4..651c20e 100644 --- a/src/soc/intel/apollolake/cpu.c +++ b/src/soc/intel/apollolake/cpu.c @@ -119,6 +119,7 @@ { X86_VENDOR_INTEL, CPUID_APOLLOLAKE_E0 }, { X86_VENDOR_INTEL, CPUID_GLK_A0 }, { X86_VENDOR_INTEL, CPUID_GLK_B0 }, + { X86_VENDOR_INTEL, CPUID_GLK_R0 }, { 0, 0 }, };
diff --git a/src/soc/intel/common/block/cpu/mp_init.c b/src/soc/intel/common/block/cpu/mp_init.c index 0a59c56..e98b5dd 100644 --- a/src/soc/intel/common/block/cpu/mp_init.c +++ b/src/soc/intel/common/block/cpu/mp_init.c @@ -70,6 +70,7 @@ { X86_VENDOR_INTEL, CPUID_APOLLOLAKE_E0 }, { X86_VENDOR_INTEL, CPUID_GLK_A0 }, { X86_VENDOR_INTEL, CPUID_GLK_B0 }, + { X86_VENDOR_INTEL, CPUID_GLK_R0 }, { X86_VENDOR_INTEL, CPUID_WHISKEYLAKE_V0 }, { X86_VENDOR_INTEL, CPUID_WHISKEYLAKE_W0 }, { X86_VENDOR_INTEL, CPUID_COFFEELAKE_U0 }, diff --git a/src/soc/intel/common/block/include/intelblocks/mp_init.h b/src/soc/intel/common/block/include/intelblocks/mp_init.h index 3c7467d..0f37a643 100644 --- a/src/soc/intel/common/block/include/intelblocks/mp_init.h +++ b/src/soc/intel/common/block/include/intelblocks/mp_init.h @@ -37,6 +37,7 @@ #define CPUID_APOLLOLAKE_E0 0x506ca #define CPUID_GLK_A0 0x706a0 #define CPUID_GLK_B0 0x706a1 +#define CPUID_GLK_R0 0x706a8 #define CPUID_WHISKEYLAKE_V0 0x806ec #define CPUID_WHISKEYLAKE_W0 0x806eb #define CPUID_COFFEELAKE_D0 0x806ea
Lijian Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32744 )
Change subject: soc/intel: Geminilake Refresh feature request support ......................................................................
Patch Set 1: Code-Review+2
Lijian Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32744 )
Change subject: soc/intel: Geminilake Refresh feature request support ......................................................................
Patch Set 1:
Only thing left is once GLK-R is published we can include the microcode as well.
Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/32744 )
Change subject: soc/intel: Geminilake Refresh feature request support ......................................................................
soc/intel: Geminilake Refresh feature request support
Add 0x706a8 for GLK Refresh CPU stepping ID.
BUG=b:132414963 BRANCH=None TEST=Image built successfully.
Signed-off-by: John Zhao john.zhao@intel.com Change-Id: I4641d9bd4c82211e7200f617cae9043b0f2f38d1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32744 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Lijian Zhao lijian.zhao@intel.com --- M src/soc/intel/apollolake/cpu.c M src/soc/intel/common/block/cpu/mp_init.c M src/soc/intel/common/block/include/intelblocks/mp_init.h 3 files changed, 3 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Lijian Zhao: Looks good to me, approved
diff --git a/src/soc/intel/apollolake/cpu.c b/src/soc/intel/apollolake/cpu.c index 11d15e4..651c20e 100644 --- a/src/soc/intel/apollolake/cpu.c +++ b/src/soc/intel/apollolake/cpu.c @@ -119,6 +119,7 @@ { X86_VENDOR_INTEL, CPUID_APOLLOLAKE_E0 }, { X86_VENDOR_INTEL, CPUID_GLK_A0 }, { X86_VENDOR_INTEL, CPUID_GLK_B0 }, + { X86_VENDOR_INTEL, CPUID_GLK_R0 }, { 0, 0 }, };
diff --git a/src/soc/intel/common/block/cpu/mp_init.c b/src/soc/intel/common/block/cpu/mp_init.c index 0a59c56..e98b5dd 100644 --- a/src/soc/intel/common/block/cpu/mp_init.c +++ b/src/soc/intel/common/block/cpu/mp_init.c @@ -70,6 +70,7 @@ { X86_VENDOR_INTEL, CPUID_APOLLOLAKE_E0 }, { X86_VENDOR_INTEL, CPUID_GLK_A0 }, { X86_VENDOR_INTEL, CPUID_GLK_B0 }, + { X86_VENDOR_INTEL, CPUID_GLK_R0 }, { X86_VENDOR_INTEL, CPUID_WHISKEYLAKE_V0 }, { X86_VENDOR_INTEL, CPUID_WHISKEYLAKE_W0 }, { X86_VENDOR_INTEL, CPUID_COFFEELAKE_U0 }, diff --git a/src/soc/intel/common/block/include/intelblocks/mp_init.h b/src/soc/intel/common/block/include/intelblocks/mp_init.h index 3c7467d..0f37a643 100644 --- a/src/soc/intel/common/block/include/intelblocks/mp_init.h +++ b/src/soc/intel/common/block/include/intelblocks/mp_init.h @@ -37,6 +37,7 @@ #define CPUID_APOLLOLAKE_E0 0x506ca #define CPUID_GLK_A0 0x706a0 #define CPUID_GLK_B0 0x706a1 +#define CPUID_GLK_R0 0x706a8 #define CPUID_WHISKEYLAKE_V0 0x806ec #define CPUID_WHISKEYLAKE_W0 0x806eb #define CPUID_COFFEELAKE_D0 0x806ea
-
John Zhao (Code Review) -
Lijian Zhao (Code Review)
-
Patrick Georgi (Code Review)