Patch set updated for coreboot: nb/amd/amdfam10: Work around sporadic lockups when CC6 enabled

[Timothy Pearson]

Timothy Pearson ([e-mail]) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12054

-gerrit

commit 6600a6bc3e1e42326a7604f02077852a1adfd982
Author: Timothy Pearson 
Date:   Thu Aug 20 15:53:25 2015 -0500

nb/amd/amdfam10: Work around sporadic lockups when CC6 enabled

The silicon in control of CC6 appears to contain minor bugs
    and / or deviations from the BKDG; through trial and error
    it was found that these issues can be worked around by reserving
    the entire possible CC6 save region, regardless of currently
    installed node count.

Change-Id: If31140651f25f9c524a824b2da552ce3690eae18
    Signed-off-by: Timothy Pearson 
---
 src/northbridge/amd/amdfam10/northbridge.c | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c
index 600fdf8..85cee13 100644
--- a/src/northbridge/amd/amdfam10/northbridge.c
+++ b/src/northbridge/amd/amdfam10/northbridge.c
@@ -810,6 +810,20 @@ static void amdfam10_domain_read_resources(device_t dev)
    		else
    			qword = 0x1000000;

+			/* FIXME
+			 * The BKDG appears to be incorrect as to the location of the CC6 save region
+			 * lower boundary on non-interleaved systems, causing lockups on attempted write
+			 * to the CC6 save region.
+			 *
+			 * For now, work around by allocating the maximum possible CC6 save region size.
+			 *
+			 * Determine if this is a BKDG error or a setup problem and remove this warning!
+			 */
+			qword = (0x1 << 27);
+			max_range_limit = (((uint64_t)(pci_read_config32(get_node_pci(max_node, 1), 0x124) & 0x1fffff)) << 27) - 1;
+
+			printk(BIOS_INFO, "Reserving CC6 save segment base: %08llx size: %08llx\n", (max_range_limit + 1), qword);
+
    		/* Reserve the CC6 save segment */
    		reserved_ram_resource(dev, 8, (max_range_limit + 1) >> 10, qword >> 10);
    	}