Change in coreboot[master]: soc/intel/cannonlake: Add Kconfig option to select UART index

[Subrata Banik (Code Review)]

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/20998

Change subject: soc/intel/cannonlake: Add Kconfig option to select UART index
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soc/intel/cannonlake: Add Kconfig option to select UART index

Cannonlake SOC has two possible ways to make serial
console functional. 1. Using 0x3F8 as Legacy UART 2. PCI
based LPSS UART2

PCI based LPSS UART2 is default enable for Chrome Design.

Change-Id: I7afa5ab2c5eb06e6df8eeb1cb1cd0de00d2b2a28
Signed-off-by: Subrata Banik 
---
M src/soc/intel/cannonlake/Kconfig
1 file changed, 7 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/20998/1

diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig
index 471fe6c..655fb7e 100644
--- a/src/soc/intel/cannonlake/Kconfig
+++ b/src/soc/intel/cannonlake/Kconfig
@@ -48,6 +48,13 @@
    select DRIVERS_UART
    select DRIVERS_UART_8250IO

+config UART_FOR_CONSOLE
+	int
+	default 2
+	help
+	    Index for UART port to use for console:
+	    0 = Legacy UART, 2 = LPSS UART2
+
 config DCACHE_RAM_BASE
    default 0xfef00000