Change in coreboot[master]: mb/intel/tglrvp: add Tiger Lake memory initialization support

[Srinidhi N Kaushik (Code Review)]

Hello Raj Astekar, Patrick Rudolph, Nick Vaccaro, Wonkyu Kim, Ravishankar Sarawadi, build bot (Jenkins), Shaunak Saha, Furquan Shaikh, Patrick Georgi, Martin Roth,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/38998

to look at the new patch set (#7).

Change subject: mb/intel/tglrvp: add Tiger Lake memory initialization support
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mb/intel/tglrvp: add Tiger Lake memory initialization support

Update memory parameters based on memory type supported by Tiger lake RVP
1. Update dq/dqs mappings and rcomp data
2. Update spd data for Tiger lake LPDDR4 SAMSUNG/MICRON memory
3. Add SPD data bin files for supported memory types
4. Update other FSPM Upds as part of memory initialization

BUG=none
BRANCH=none
TEST= build tglrvp flash and boot to kernel

Signed-off-by: Srinidhi N Kaushik 
Change-Id: I7248862efd1dcd5a0df0e17d39b44c168caa200e
---
M src/mainboard/intel/tglrvp/board_id.h
M src/mainboard/intel/tglrvp/romstage_fsp_params.c
A src/mainboard/intel/tglrvp/spd/Hynix-H9HKNNNEBMAV-4267.spd.hex
M src/mainboard/intel/tglrvp/spd/Makefile.inc
A src/mainboard/intel/tglrvp/spd/Micron-MT53D1G64D8SQ-046.spd.hex
A src/mainboard/intel/tglrvp/spd/Samsung-K4UBE3D4AA-MGCL.spd.hex
M src/mainboard/intel/tglrvp/spd/spd.h
M src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/variants.h
M src/mainboard/intel/tglrvp/variants/tglrvp_up3/Makefile.inc
A src/mainboard/intel/tglrvp/variants/tglrvp_up3/memory.c
M src/soc/intel/tigerlake/include/soc/meminit_tgl.h
11 files changed, 313 insertions(+), 19 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/38998/7