Patch set updated for coreboot: soc/intel/skylake: Pass proper CPU flex ratio override

[Naresh Solanki]

Naresh Solanki ([e-mail]) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17555

-gerrit

commit fe49718d8709cbc7e9a379b4ef9b205864cf5137
Author: Naresh G Solanki 
Date:   Wed Nov 16 21:34:41 2016 +0530

soc/intel/skylake: Pass proper CPU flex ratio override

In bootblock, cpu flex ratio is set to TDP nomial.
    When not supplied with CPU flex ratio override of TDP nominal(as set in
    bootblock) to FSP, then FSP by default tries to set it zero & gives
    reset.

Set FSP UPD for CPU flex ratio override to that set in bootblock to
    avoid reset.

Change-Id: I8cae5530ec97cedfbd71771f291db6f55a9fd5c2
    Signed-off-by: Rizwan Qureshi 
    Signed-off-by: Subrata Banik 
    Signed-off-by: Naresh G Solanki 
---
 src/soc/intel/skylake/romstage/romstage_fsp20.c | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/src/soc/intel/skylake/romstage/romstage_fsp20.c b/src/soc/intel/skylake/romstage/romstage_fsp20.c
index 8e08323..7752255 100644
--- a/src/soc/intel/skylake/romstage/romstage_fsp20.c
+++ b/src/soc/intel/skylake/romstage/romstage_fsp20.c
@@ -19,12 +19,14 @@
 #include <arch/symbols.h>
 #include <assert.h>
 #include <cpu/x86/mtrr.h>
+#include <cpu/x86/msr.h>
 #include <cbmem.h>
 #include <chip.h>
 #include <console/console.h>
 #include <device/pci_def.h>
 #include <fsp/util.h>
 #include <fsp/memmap.h>
+#include <soc/msr.h>
 #include <soc/pci_devs.h>
 #include <soc/pm.h>
 #include <soc/romstage.h>
@@ -94,6 +96,17 @@ asmlinkage void *car_stage_c_entry(void)
    return postcar_commit_mtrrs(&pcf);
 }

+static void cpu_flex_override(FSP_M_CONFIG *m_cfg)
+{
+	msr_t flex_ratio;
+	m_cfg->CpuRatioOverride = 1;
+	/* Set cpuratio to that we set in bootblock, This will ensure fspm know
+	 * what flex ratio we intend to use.
+	 */
+	flex_ratio = rdmsr(MSR_FLEX_RATIO);
+	m_cfg->CpuRatio = (flex_ratio.lo >> 8) & 0xff;
+}
+
 static void soc_memory_init_params(FSP_M_CONFIG *m_cfg)
 {
    const struct device *dev;
@@ -130,6 +143,8 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg)
    		mask |= (1<<i);
    }
    m_cfg->PcieRpEnableMask = mask;
+
+	cpu_flex_override(m_cfg);
 }

void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd)