Change in coreboot[master]: google/kahlee: Create mainboard_pirq_data

[Richard Spiegel (Code Review)]

Richard Spiegel has posted comments on this change. ( https://review.coreboot.org/22940 )

Change subject: google/kahlee: Create mainboard_pirq_data
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Patch Set 1:

Local test results:
PCI IRQ: Found device 0:01.00 using PIN A
PCI Devfn (0x8) not found in pirq_data table
GFX does not has interrupt.
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PCI IRQ: Found device 0:08.00 using PIN A
PCI Devfn (0x40) not found in pirq_data table
PSP does not has interrupt.
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PCI IRQ: Found device 0:11.00 using PIN A
    Found this device in pirq_data table entry 8
Got IRQ 0x1F (disabled), perhaps this device was defined wrong?
SATA PIC mode wrong in mainboard_picr_data[]
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PCI IRQ: Found device 0:14.07 using PIN A
    Found this device in pirq_data table entry 6
Got IRQ 0x1F (disabled), perhaps this device was defined wrong?
SD PIC mode wrong in mainboard_picr_data[]
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Is PIC mode important? I believe Chromium uses APIC mode.