Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46720 )
Change subject: {cpu,nb}/intel/haswell: Drop unnecessary `UL` suffix ......................................................................
{cpu,nb}/intel/haswell: Drop unnecessary `UL` suffix
Tested with BUILD_TIMELESS=1, Google Wolf does not change.
Change-Id: I029ab0dccbf7b61d641cccf79b491fabf97ab74a Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/cpu/intel/haswell/haswell.h M src/northbridge/intel/haswell/finalize.c M src/northbridge/intel/haswell/gma.c M src/northbridge/intel/haswell/northbridge.c 4 files changed, 8 insertions(+), 8 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/46720/1
diff --git a/src/cpu/intel/haswell/haswell.h b/src/cpu/intel/haswell/haswell.h index fd1ce9e..e0e1e1c 100644 --- a/src/cpu/intel/haswell/haswell.h +++ b/src/cpu/intel/haswell/haswell.h @@ -84,7 +84,7 @@
/* PCODE MMIO communications live in the MCHBAR. */ #define BIOS_MAILBOX_INTERFACE 0x5da4 -#define MAILBOX_RUN_BUSY (1UL << 31) +#define MAILBOX_RUN_BUSY (1 << 31) #define MAILBOX_BIOS_CMD_READ_PCS 1 #define MAILBOX_BIOS_CMD_WRITE_PCS 2 #define MAILBOX_BIOS_CMD_READ_CALIBRATION 0x509 diff --git a/src/northbridge/intel/haswell/finalize.c b/src/northbridge/intel/haswell/finalize.c index 1600a42..b95b3fe 100644 --- a/src/northbridge/intel/haswell/finalize.c +++ b/src/northbridge/intel/haswell/finalize.c @@ -22,10 +22,10 @@
MCHBAR32_OR(MMIO_PAVP_MSG, 1 << 0); /* PAVP */ MCHBAR32_OR(PCU_DDR_PTM_CTL, 1 << 5); /* DDR PTM */ - MCHBAR32_OR(DMIVCLIM, 1UL << 31); + MCHBAR32_OR(DMIVCLIM, 1 << 31); MCHBAR32_OR(CRDTLCK, 1 << 0); MCHBAR32_OR(MCARBLCK, 1 << 0); - MCHBAR32_OR(REQLIM, 1UL << 31); + MCHBAR32_OR(REQLIM, 1 << 31); MCHBAR32_OR(UMAGFXCTL, 1 << 0); /* UMA GFX */ MCHBAR32_OR(VTDTRKLCK, 1 << 0); /* VTDTRK */
diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c index 66c8d2d..0bca230 100644 --- a/src/northbridge/intel/haswell/gma.c +++ b/src/northbridge/intel/haswell/gma.c @@ -196,7 +196,7 @@ gtt_write_regs(haswell_gt_setup);
/* Wait for Mailbox Ready */ - gtt_poll(0x138124, (1UL << 31), (0UL << 31)); + gtt_poll(0x138124, (1 << 31), (0 << 31));
/* Mailbox Data - RC6 VIDS */ gtt_write(0x138128, 0x00000000); @@ -205,7 +205,7 @@ gtt_write(0x138124, 0x80000004);
/* Wait for Mailbox Ready */ - gtt_poll(0x138124, (1UL << 31), (0UL << 31)); + gtt_poll(0x138124, (1 << 31), (0 << 31));
/* Enable PM Interrupts */ gtt_write(GEN6_PMIER, GEN6_PM_MBOX_EVENT | GEN6_PM_THERMAL_EVENT | diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c index 88ccd71..2d19ccd 100644 --- a/src/northbridge/intel/haswell/northbridge.c +++ b/src/northbridge/intel/haswell/northbridge.c @@ -31,18 +31,18 @@
switch ((pciexbar_reg >> 1) & 3) { case 0: /* 256MB */ - mask = (1UL << 31) | (1 << 30) | (1 << 29) | (1 << 28); + mask = (1 << 31) | (1 << 30) | (1 << 29) | (1 << 28); *base = pciexbar_reg & mask; *len = 256 * 1024 * 1024; return 1; case 1: /* 128M */ - mask = (1UL << 31) | (1 << 30) | (1 << 29) | (1 << 28); + mask = (1 << 31) | (1 << 30) | (1 << 29) | (1 << 28); mask |= (1 << 27); *base = pciexbar_reg & mask; *len = 128 * 1024 * 1024; return 1; case 2: /* 64M */ - mask = (1UL << 31) | (1 << 30) | (1 << 29) | (1 << 28); + mask = (1 << 31) | (1 << 30) | (1 << 29) | (1 << 28); mask |= (1 << 27) | (1 << 26); *base = pciexbar_reg & mask; *len = 64 * 1024 * 1024;
Hello Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46720
to look at the new patch set (#2).
Change subject: {cpu,nb}/intel/haswell: Drop unnecessary `UL` suffix ......................................................................
{cpu,nb}/intel/haswell: Drop unnecessary `UL` suffix
Tested with BUILD_TIMELESS=1, Google Wolf does not change.
Change-Id: I029ab0dccbf7b61d641cccf79b491fabf97ab74a Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/cpu/intel/haswell/haswell.h M src/northbridge/intel/haswell/finalize.c M src/northbridge/intel/haswell/gma.c M src/northbridge/intel/haswell/northbridge.c 4 files changed, 8 insertions(+), 8 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/46720/2
Hello build bot (Jenkins), Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46720
to look at the new patch set (#4).
Change subject: {cpu,nb}/intel/haswell: Drop unnecessary `UL` suffix ......................................................................
{cpu,nb}/intel/haswell: Drop unnecessary `UL` suffix
Tested with BUILD_TIMELESS=1, Google Wolf does not change.
Change-Id: I029ab0dccbf7b61d641cccf79b491fabf97ab74a Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/cpu/intel/haswell/haswell.h M src/northbridge/intel/haswell/finalize.c M src/northbridge/intel/haswell/gma.c M src/northbridge/intel/haswell/northbridge.c 4 files changed, 8 insertions(+), 8 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/46720/4
Hello build bot (Jenkins), Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46720
to look at the new patch set (#7).
Change subject: {cpu,nb}/intel/haswell: Drop unnecessary `UL` suffix ......................................................................
{cpu,nb}/intel/haswell: Drop unnecessary `UL` suffix
Tested with BUILD_TIMELESS=1, Google Wolf does not change.
Change-Id: I029ab0dccbf7b61d641cccf79b491fabf97ab74a Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/cpu/intel/haswell/haswell.h M src/northbridge/intel/haswell/finalize.c M src/northbridge/intel/haswell/gma.c M src/northbridge/intel/haswell/northbridge.c 4 files changed, 8 insertions(+), 8 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/46720/7
Hello build bot (Jenkins), Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46720
to look at the new patch set (#9).
Change subject: {cpu,nb}/intel/haswell: Drop unnecessary `UL` suffix ......................................................................
{cpu,nb}/intel/haswell: Drop unnecessary `UL` suffix
Tested with BUILD_TIMELESS=1, Google Wolf does not change.
Change-Id: I029ab0dccbf7b61d641cccf79b491fabf97ab74a Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/cpu/intel/haswell/haswell.h M src/northbridge/intel/haswell/finalize.c M src/northbridge/intel/haswell/gma.c M src/northbridge/intel/haswell/northbridge.c 4 files changed, 8 insertions(+), 8 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/46720/9
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46720 )
Change subject: {cpu,nb}/intel/haswell: Drop unnecessary `UL` suffix ......................................................................
Patch Set 14: Code-Review+2
Michael Niewöhner has submitted this change. ( https://review.coreboot.org/c/coreboot/+/46720 )
Change subject: {cpu,nb}/intel/haswell: Drop unnecessary `UL` suffix ......................................................................
{cpu,nb}/intel/haswell: Drop unnecessary `UL` suffix
Tested with BUILD_TIMELESS=1, Google Wolf does not change.
Change-Id: I029ab0dccbf7b61d641cccf79b491fabf97ab74a Signed-off-by: Angel Pons th3fanbus@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/46720 Reviewed-by: Michael Niewöhner foss@mniewoehner.de Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/cpu/intel/haswell/haswell.h M src/northbridge/intel/haswell/finalize.c M src/northbridge/intel/haswell/gma.c M src/northbridge/intel/haswell/northbridge.c 4 files changed, 8 insertions(+), 8 deletions(-)
Approvals: build bot (Jenkins): Verified Michael Niewöhner: Looks good to me, approved
diff --git a/src/cpu/intel/haswell/haswell.h b/src/cpu/intel/haswell/haswell.h index fd1ce9e..e0e1e1c 100644 --- a/src/cpu/intel/haswell/haswell.h +++ b/src/cpu/intel/haswell/haswell.h @@ -84,7 +84,7 @@
/* PCODE MMIO communications live in the MCHBAR. */ #define BIOS_MAILBOX_INTERFACE 0x5da4 -#define MAILBOX_RUN_BUSY (1UL << 31) +#define MAILBOX_RUN_BUSY (1 << 31) #define MAILBOX_BIOS_CMD_READ_PCS 1 #define MAILBOX_BIOS_CMD_WRITE_PCS 2 #define MAILBOX_BIOS_CMD_READ_CALIBRATION 0x509 diff --git a/src/northbridge/intel/haswell/finalize.c b/src/northbridge/intel/haswell/finalize.c index 1600a42..b95b3fe 100644 --- a/src/northbridge/intel/haswell/finalize.c +++ b/src/northbridge/intel/haswell/finalize.c @@ -22,10 +22,10 @@
MCHBAR32_OR(MMIO_PAVP_MSG, 1 << 0); /* PAVP */ MCHBAR32_OR(PCU_DDR_PTM_CTL, 1 << 5); /* DDR PTM */ - MCHBAR32_OR(DMIVCLIM, 1UL << 31); + MCHBAR32_OR(DMIVCLIM, 1 << 31); MCHBAR32_OR(CRDTLCK, 1 << 0); MCHBAR32_OR(MCARBLCK, 1 << 0); - MCHBAR32_OR(REQLIM, 1UL << 31); + MCHBAR32_OR(REQLIM, 1 << 31); MCHBAR32_OR(UMAGFXCTL, 1 << 0); /* UMA GFX */ MCHBAR32_OR(VTDTRKLCK, 1 << 0); /* VTDTRK */
diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c index 66c8d2d..0bca230 100644 --- a/src/northbridge/intel/haswell/gma.c +++ b/src/northbridge/intel/haswell/gma.c @@ -196,7 +196,7 @@ gtt_write_regs(haswell_gt_setup);
/* Wait for Mailbox Ready */ - gtt_poll(0x138124, (1UL << 31), (0UL << 31)); + gtt_poll(0x138124, (1 << 31), (0 << 31));
/* Mailbox Data - RC6 VIDS */ gtt_write(0x138128, 0x00000000); @@ -205,7 +205,7 @@ gtt_write(0x138124, 0x80000004);
/* Wait for Mailbox Ready */ - gtt_poll(0x138124, (1UL << 31), (0UL << 31)); + gtt_poll(0x138124, (1 << 31), (0 << 31));
/* Enable PM Interrupts */ gtt_write(GEN6_PMIER, GEN6_PM_MBOX_EVENT | GEN6_PM_THERMAL_EVENT | diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c index 88ccd71..2d19ccd 100644 --- a/src/northbridge/intel/haswell/northbridge.c +++ b/src/northbridge/intel/haswell/northbridge.c @@ -31,18 +31,18 @@
switch ((pciexbar_reg >> 1) & 3) { case 0: /* 256MB */ - mask = (1UL << 31) | (1 << 30) | (1 << 29) | (1 << 28); + mask = (1 << 31) | (1 << 30) | (1 << 29) | (1 << 28); *base = pciexbar_reg & mask; *len = 256 * 1024 * 1024; return 1; case 1: /* 128M */ - mask = (1UL << 31) | (1 << 30) | (1 << 29) | (1 << 28); + mask = (1 << 31) | (1 << 30) | (1 << 29) | (1 << 28); mask |= (1 << 27); *base = pciexbar_reg & mask; *len = 128 * 1024 * 1024; return 1; case 2: /* 64M */ - mask = (1UL << 31) | (1 << 30) | (1 << 29) | (1 << 28); + mask = (1 << 31) | (1 << 30) | (1 << 29) | (1 << 28); mask |= (1 << 27) | (1 << 26); *base = pciexbar_reg & mask; *len = 64 * 1024 * 1024;
-
Angel Pons (Code Review) -
Michael Niewöhner (Code Review)