Change in coreboot[master]: mb/amd/chausie/devicetree: update PCI root ports

[Felix Held (Code Review)]

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63162 )

Change subject: mb/amd/chausie/devicetree: update PCI root ports
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mb/amd/chausie/devicetree: update PCI root ports

Only enable the PCIe root ports that have corresponding DXIO descriptors
and also update the comments to have them match the actual hardware
configuration.

Signed-off-by: Felix Held 
Change-Id: I378c620abb6e52de680669b6edd228874153e399
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63162
Reviewed-by: Raul Rangel 
Reviewed-by: Fred Reitberger 
Tested-by: build bot (Jenkins) 
---
M src/mainboard/amd/chausie/devicetree.cb
1 file changed, 3 insertions(+), 6 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Raul Rangel: Looks good to me, approved
  Fred Reitberger: Looks good to me, but someone else must approve

diff --git a/src/mainboard/amd/chausie/devicetree.cb b/src/mainboard/amd/chausie/devicetree.cb
index 7f37be2..85e9c08 100644
--- a/src/mainboard/amd/chausie/devicetree.cb
+++ b/src/mainboard/amd/chausie/devicetree.cb
@@ -28,12 +28,9 @@

device domain 0 on
    	device ref iommu on end
-		device ref gpp_bridge_0 on end # NVMe
-		device ref gpp_bridge_1 on end
-		device ref gpp_bridge_2 on end # WWAN
-		device ref gpp_bridge_3 on end # LAN
-		device ref gpp_bridge_4 on end # WLAN
-		device ref gpp_bridge_5 on end
+		device ref gpp_bridge_0 on end # GBE
+		device ref gpp_bridge_1 on end # WIFI
+		device ref gpp_bridge_2 on end # NVMe SSD
    	device ref gpp_bridge_a on  # Internal GPP Bridge 0 to Bus A
    		device ref gfx on end # Internal GPU (GFX)
    		device ref gfx_hda on end # Display HD Audio Controller (GFXAZ)