[XS] Change in coreboot[main]: mb/google/fatcat/var/fatcat: disable ISH UART0 RX pin

[Li1 Feng (Code Review)]

Attention is currently required from: Bora Guvendik, Jayvik Desai, Jérémy Compostella, Kapil Porwal, Li1 Feng, Pranava Y N.

Hello Bora Guvendik, Jayvik Desai, Jérémy Compostella, Kapil Porwal, Pranava Y N, Subrata Banik, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/86005?usp=email

to look at the new patch set (#5).

Change subject: mb/google/fatcat/var/fatcat: disable ISH UART0 RX pin
......................................................................

mb/google/fatcat/var/fatcat: disable ISH UART0 RX pin

On PTL RVP, ISH shares UART with FPS, we can enable either ISH UART or
FPS UART, or disable both UART by changing the DIP switch settings. When
DIP switch is not set for ISH, ISH RX signal is disconnected, causing
ISH low power mode failure. Therefore, NC ISH RX pin mux to minimize the
impact on ISH PM. As a result, ISH console won't accept input since this
pin is not connected.

TEST=PTL RVP H1 DB, DIP SW1317 3-6, 4-5 ON to enable FPS UART, ISH main
firmware boots up and runs successfully.
SW1317 all switches OFF to disable both FPS and ISH UART, ISH main
firmware boots up and runs successfully.

Change-Id: Ic84f8ead6a1fd056e649edbb1471bcb913a0a09a
Signed-off-by: Li Feng 
---
M src/mainboard/google/fatcat/variants/fatcat/fw_config.c
M src/mainboard/google/fatcat/variants/fatcat/gpio.c
2 files changed, 2 insertions(+), 4 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/86005/5