Attention is currently required from: Furquan Shaikh, Ravishankar Sarawadi, Duncan Laurie, Alex Levin, Sukumar Ghorai, Raj Astekar, Patrick Rudolph, Shreesh Chhabbi.
Hello build bot (Jenkins), Furquan Shaikh, Ravishankar Sarawadi, Duncan Laurie, Alex Levin, Duncan Laurie, Sukumar Ghorai, Raj Astekar, Patrick Rudolph, Shreesh Chhabbi,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/49766
to look at the new patch set (#26).
Change subject: soc/intel/tgl: Configure S0ix substates
......................................................................
soc/intel/tgl: Configure S0ix substates
In this change, S0ix substates are enabled or disabled based on
mainboard design. Implementation is as follows.
1. If platform is based on tgl up3, disable S0i3.3, S0i3.4 and S0i2.2
2. If external bypass is not used, disable S0i3.x is disabled
3. If external clock gating is not implemented, S0i3.4 is disabled
4. If external phy gating is not implemented, disable S0i3.3, S0i3.4 and S0i2.2
5. If CNVi or ISH is not used, disable S0i3.2, S0i3.3 & S0i3.4
BUG=b:177821896
TEST=Build coreboot for volteer
Signed-off-by: Shreesh Chhabbi shreesh.chhabbi@intel.corp-partner.google.com
Change-Id: I5f2ac8b72d0c9b05bc02c092188d0c742cc83af9
---
M src/soc/intel/tigerlake/chip.h
M src/soc/intel/tigerlake/fsp_params.c
2 files changed, 75 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/49766/26
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Gerrit-Project: coreboot
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Gerrit-Change-Id: I5f2ac8b72d0c9b05bc02c092188d0c742cc83af9
Gerrit-Change-Number: 49766
Gerrit-PatchSet: 26
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