[L] Change in coreboot[master]: mb/intel/adlrvp: Add ADL-S DDR5 UDIMM 1DPC

[Maximilian Brune (Code Review)]

Attention is currently required from: Paul Menzel, Tim Wawrzynczak, Angel Pons, Lean Sheng Tan.

Hello build bot (Jenkins), Tim Wawrzynczak, Angel Pons, Lean Sheng Tan,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/66545

to look at the new patch set (#19).

Change subject: mb/intel/adlrvp: Add ADL-S DDR5 UDIMM 1DPC
......................................................................

mb/intel/adlrvp: Add ADL-S DDR5 UDIMM 1DPC

Tested:
- Boot SeaBIOS (46de2eecf) -> Linux 6.0.1
- Boot 9elements/EDK2 (4f58f36b8) -> Linux 6.0.1, Windows 10
- M.2 SSD Slot 1: PCH SSD
- M.2 SSD Slot 2: PCH SSD
- M.2 SSD Slot 3: PCH SSD, Backside
- SATA Cable Port 1-3
- SATA Direct Connect Port
- DisplayPort Port 1,2
- HDMI Port 1,2
- PCIE x4 Slot 1
- PCIE x4 Slot 3
- USB Ports 1-4 (Backpanel)
- M.2. CNVI: WiFi (Linux 6.0.1 works, Win 10 does not)
- S3 (suspend to ram) (Linux 6.0.1 works, Win 10 does not)
- S4 (hibernate)
- M.2. CNVI: Bluetooth
- LAN GBE

missing:
- Displayport over USB-C
- some USB Ports still missing
- PCIE x4 Slot 2 (for some reason it doesn't work)
- M.2 SSD Slot 4: CPU SSD
- PEG (PCIE x16 Slot) connected to CPU

Signed-off-by: Maximilian Brune 
Change-Id: Ic1f62d6dd0b00d26f8c8a71b624ba5fba4c63774
---
M src/mainboard/intel/adlrvp/Kconfig
M src/mainboard/intel/adlrvp/Kconfig.name
M src/mainboard/intel/adlrvp/Makefile.inc
A src/mainboard/intel/adlrvp/devicetree_s.cb
A src/mainboard/intel/adlrvp/early_gpio_s.c
A src/mainboard/intel/adlrvp/gpio_s.c
M src/mainboard/intel/adlrvp/include/baseboard/variants.h
M src/mainboard/intel/adlrvp/memory.c
M src/mainboard/intel/adlrvp/ramstage.c
M src/mainboard/intel/adlrvp/romstage_fsp_params.c
A src/mainboard/intel/adlrvp/variants/adlrvp_s_ddr5_udimm_1dpc/overridetree.cb
11 files changed, 747 insertions(+), 9 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/66545/19