Change in coreboot[master]: soc/intel/common/block/cse: Add check before heci_reset() in heci_init()

[Subrata Banik (Code Review)]

Attention is currently required from: Matt DeVillier, Tim Wawrzynczak, Paul Menzel, Angel Pons, Sridhar Siricilla, Patrick Rudolph.
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61304 )

Change subject: soc/intel/common/block/cse: Add check before heci_reset() in heci_init()
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Patch Set 3:

(1 comment)

File src/soc/intel/common/block/cse/cse.c:

https://review.coreboot.org/c/coreboot/+/61304/comment/963be151_0e4611bc 
PS3, Line 96:
> > IMO, you just need one check where if CSE device is on PCI Bus (DID/VID is not 0xFFFF) for now to solve this problem.
>
> actually, that doesn't work it seems. On a Librem 13v2 with a HAP disabled/neutralized ME (via ME cleaner), reading the VID/DID registers still returns valid values, even with the HECI device disabled in devicetree.

I have almost forgot the purpose of HAP mode but you are right, it's not like function disable. I thought you had function disable use case.
> Guarding heci_init() with is_cse_enabled() at the top of the function does however return correctly and prevent the ~15s timeout from heci_reset()

if you have HAP disable then to reflect the same, you might need to always disable HECI in devicetree to use as an indicator. Then as you said, a guard against heci_init() is what we need.