[S] Change in coreboot[master]: soc/intel/meteorlake: transition full control over PM Timer from FSP ...

[Kapil Porwal (Code Review)]

Attention is currently required from: Tarun Tuli, Kapil Porwal.

Hello build bot (Jenkins), Tarun Tuli, Subrata Banik,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/69613

to look at the new patch set (#4).

Change subject: soc/intel/meteorlake: transition full control over PM Timer from FSP to coreboot
......................................................................

soc/intel/meteorlake: transition full control over PM Timer from FSP to coreboot

Set `EnableTcoTimer=1` in order to keep FSP from
 1) enabling ACPI Timer emulation in uCode.
 2) disabling the PM ACPI Timer.

Both actions are now done in coreboot.

`EnableTcoTimer=1` makes FSP skip these steps in any possible case
including `SkipMpInit=0`, `SkipMpInit=1`, use of the MP PPI or FSP
Multiphase Init. This way full control is left to coreboot.

Port of commit 0e905801f8ff ("soc/intel: transition full control over PM
Timer from FSP to coreboot").

NOTE: This will have a huge power impact when it's enabled. If TCO timer
is disabled, uCode ACPI timer emulation must be enabled, and WDAT table
must not be exposed to the OS.

BUG=none
TEST=Boot to OS on google/rex.

Excerpt from google/rex coreboot log:
[SPEW ]   EnableTcoTimer                      = 1

Signed-off-by: Kapil Porwal 
Change-Id: I2693f0390e6c9fa92fec366ab87589c3bcea9027
---
M src/soc/intel/meteorlake/fsp_params.c
1 file changed, 47 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/69613/4