Change in coreboot[master]: HACK: Limit SPI NOR size to 8MB

[Ravi kumar (Code Review)]

Attention is currently required from: Sajida Bhanu.
Hello Sajida Bhanu,

I'd like you to do a code review. Please visit

https://review.coreboot.org/c/coreboot/+/50885

to review the following change.

Change subject: HACK: Limit SPI NOR size to 8MB
......................................................................

HACK: Limit SPI NOR size to 8MB

Limit SPI NOR size to 8MB to match with coreboot rom size by changing
number of sectors.

Change-Id: I66aa915aca7e68537563c6e05d4936afea32d7ea
Signed-off-by: Shaik Sajida Bhanu 
---
M src/drivers/spi/macronix.c
1 file changed, 1 insertion(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/50885/1

diff --git a/src/drivers/spi/macronix.c b/src/drivers/spi/macronix.c
index 69e7a9f..c0ab0c8 100644
--- a/src/drivers/spi/macronix.c
+++ b/src/drivers/spi/macronix.c
@@ -101,7 +101,7 @@
    {
    	/* MX25U51245G */
    	.id[0] = 0x253a,
-		.nr_sectors_shift = 14,
+		.nr_sectors_shift = 11,
    },
    {
    	/* MX25L12855E */