New patch to review for coreboot: sb/intel/common/gpio: Support ICH9M and prior

[Patrick Rudolph]

Patrick Rudolph ([e-mail]) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18012

-gerrit

commit 64daa0557c26325c22a1ef497a68d785165e3d1d
Author: Patrick Rudolph 
Date:   Mon Jan 2 18:41:37 2017 +0100

sb/intel/common/gpio: Support ICH9M and prior

Reorder the commands executed to support ICH9M and prior where
    GPIO level and direction are only set on pins configured as GPIO.
    Required to set correct GPIO layout on T500.

Tested on T500.

Change-Id: I691e672c7cb52ca51a80fd29657ada7488db0d41
    Signed-off-by: Patrick Rudolph 
---
 src/southbridge/intel/common/gpio.c | 16 ++++++++++------
 1 file changed, 10 insertions(+), 6 deletions(-)

diff --git a/src/southbridge/intel/common/gpio.c b/src/southbridge/intel/common/gpio.c
index aadd519..c07a5bc 100644
--- a/src/southbridge/intel/common/gpio.c
+++ b/src/southbridge/intel/common/gpio.c
@@ -37,13 +37,17 @@ void setup_pch_gpios(const struct pch_gpio_map *gpio)
 {
    u16 gpiobase = get_gpio_base();

+	/* The order of these calls does matter on ICH9M and prior.
+	 * The direction and level are only set on pins configured as GPIO,
+	 * thus make sure that mode register is written first !*/
+
    /* GPIO Set 1 */
-	if (gpio->set1.level)
-		outl(*((u32 *)gpio->set1.level), gpiobase + GP_LVL);
    if (gpio->set1.mode)
    	outl(*((u32 *)gpio->set1.mode), gpiobase + GPIO_USE_SEL);
    if (gpio->set1.direction)
    	outl(*((u32 *)gpio->set1.direction), gpiobase + GP_IO_SEL);
+	if (gpio->set1.level)
+		outl(*((u32 *)gpio->set1.level), gpiobase + GP_LVL);
    if (gpio->set1.reset)
    	outl(*((u32 *)gpio->set1.reset), gpiobase + GP_RST_SEL1);
    if (gpio->set1.invert)
@@ -52,22 +56,22 @@ void setup_pch_gpios(const struct pch_gpio_map *gpio)
    	outl(*((u32 *)gpio->set1.blink), gpiobase + GPO_BLINK);

/* GPIO Set 2 */
-	if (gpio->set2.level)
-		outl(*((u32 *)gpio->set2.level), gpiobase + GP_LVL2);
    if (gpio->set2.mode)
    	outl(*((u32 *)gpio->set2.mode), gpiobase + GPIO_USE_SEL2);
    if (gpio->set2.direction)
    	outl(*((u32 *)gpio->set2.direction), gpiobase + GP_IO_SEL2);
+	if (gpio->set2.level)
+		outl(*((u32 *)gpio->set2.level), gpiobase + GP_LVL2);
    if (gpio->set2.reset)
    	outl(*((u32 *)gpio->set2.reset), gpiobase + GP_RST_SEL2);

/* GPIO Set 3 */
-	if (gpio->set3.level)
-		outl(*((u32 *)gpio->set3.level), gpiobase + GP_LVL3);
    if (gpio->set3.mode)
    	outl(*((u32 *)gpio->set3.mode), gpiobase + GPIO_USE_SEL3);
    if (gpio->set3.direction)
    	outl(*((u32 *)gpio->set3.direction), gpiobase + GP_IO_SEL3);
+	if (gpio->set3.level)
+		outl(*((u32 *)gpio->set3.level), gpiobase + GP_LVL3);
    if (gpio->set3.reset)
    	outl(*((u32 *)gpio->set3.reset), gpiobase + GP_RST_SEL3);
 }