Francois Toguo Fotso has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49943 )
Change subject: This change implements CrashLog for intel TGL. ......................................................................
This change implements CrashLog for intel TGL.
Signed-off-by: Francois Toguo francois.toguo.fotso@intel.com Change-Id: Ie3763cebcd1178709cc8597710bf062a30901809 --- M src/soc/intel/common/block/include/intelblocks/pmc_ipc.h M src/soc/intel/tigerlake/Kconfig M src/soc/intel/tigerlake/Makefile.inc M src/soc/intel/tigerlake/acpi.c A src/soc/intel/tigerlake/crashlog_lib.c A src/soc/intel/tigerlake/include/soc/crashlog_def.h A src/soc/intel/tigerlake/include/soc/crashlog_lib.h M src/soc/intel/tigerlake/include/soc/iomap.h M src/soc/intel/tigerlake/include/soc/pci_devs.h M src/soc/intel/tigerlake/romstage/fsp_params.c M src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h 11 files changed, 1,011 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/49943/1
diff --git a/src/soc/intel/common/block/include/intelblocks/pmc_ipc.h b/src/soc/intel/common/block/include/intelblocks/pmc_ipc.h index 71adf5b..b67abc0 100644 --- a/src/soc/intel/common/block/include/intelblocks/pmc_ipc.h +++ b/src/soc/intel/common/block/include/intelblocks/pmc_ipc.h @@ -17,7 +17,7 @@ #define PMC_IPC_CMD_SIZE_MASK 0xff
#define PMC_IPC_CMD_FIELD(name, val) \ - (((val) & PMC_IPC_CMD_##name##_MASK << PMC_IPC_CMD_##name##_SHIFT)) + ((((val) & PMC_IPC_CMD_##name##_MASK) << PMC_IPC_CMD_##name##_SHIFT))
#define PMC_IPC_CMD_NO_MSI 0
diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index 8211d56..8ce7954 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -263,4 +263,15 @@ int default 16
+config ACPI_BERT + bool "Enables ACPI BERT" + default y + help + Enables ACPI Boot Error Record Table generation. + +config SOC_INTEL_CRASHLOG + def_bool n + help + Enables CrashLog. + endif diff --git a/src/soc/intel/tigerlake/Makefile.inc b/src/soc/intel/tigerlake/Makefile.inc index 4a41812..d87758f 100644 --- a/src/soc/intel/tigerlake/Makefile.inc +++ b/src/soc/intel/tigerlake/Makefile.inc @@ -46,6 +46,7 @@ ramstage-y += systemagent.c ramstage-y += me.c ramstage-y += xhci.c +ramstage-y += crashlog_lib.c
smm-y += gpio.c smm-y += p2sb.c diff --git a/src/soc/intel/tigerlake/acpi.c b/src/soc/intel/tigerlake/acpi.c index cb1731f..a7ee474 100644 --- a/src/soc/intel/tigerlake/acpi.c +++ b/src/soc/intel/tigerlake/acpi.c @@ -12,6 +12,9 @@ #include <intelblocks/cpulib.h> #include <intelblocks/pmclib.h> #include <intelblocks/acpi.h> +#include <arch/bert_storage.h> +#include <soc/crashlog_def.h> +#include <soc/crashlog_lib.h> #include <soc/cpu.h> #include <soc/iomap.h> #include <soc/nvs.h> @@ -341,3 +344,89 @@ { return acpigen_soc_gpio_op("\_SB.PCI0.CTXS", gpio_num); } + +void acpi_soc_fill_bert(acpi_bert_t *bert, + void **region, + size_t *length) +{ + acpi_generic_error_status_t *status = NULL; + size_t cpu_record_size, pmc_record_size; + void *cl_data = NULL; + + if (!crashlog_get_total_data_size()) { + printk(BIOS_ERR, "Error: No crashlog record present\n"); + return; + } + + status = bert_new_event(&CPER_SEC_FW_ERR_REC_REF_GUID); + if (!status) { + printk(BIOS_ERR, "Error: unable to allocate GSB\n"); + return; + } + + if (crashlog_get_total_data_size() > bert_storage_remaining()) { + printk(BIOS_ERR, "Error: Crashlog entry would exceed " + "available region\n"); + return; + } + + cpu_record_size = crashlog_get_cpu_record_size(); + if (cpu_record_size) { + cl_data = new_cper_fw_error_crashlog(status, cpu_record_size); + if (!cl_data) { + printk(BIOS_ERR, "Error: Crashlog CPU entry(size %lu) " + "would exceed available region\n", + cpu_record_size); + return; + } + printk(BIOS_DEBUG, "cl_data %p, cpu_record_size %lu\n", + cl_data, cpu_record_size); + crashlog_fill_cpu_records(cl_data); + } + + pmc_record_size = crashlog_get_pmc_record_size(); + if (pmc_record_size) { + /* Allocate new FW ERR structure in case CPU crashlog is present */ + if (cpu_record_size && !bert_append_fw_err(status)) { + printk(BIOS_ERR, "Error: Crashlog PMC entry would " + "exceed available region\n"); + return; + } + + cl_data = new_cper_fw_error_crashlog(status, pmc_record_size); + if (!cl_data) { + printk(BIOS_ERR, "Error: Crashlog PMC entry(size %lu) " + "would exceed available region\n", + pmc_record_size); + return; + } + printk(BIOS_DEBUG, "cl_data %p, pmc_record_size %lu\n", + cl_data, pmc_record_size); + crashlog_fill_pmc_records(cl_data); + } + + *length = status->raw_data_length; + *region = (void *)status; + +} + +bool acpi_is_boot_error_src_present(void) +{ + + if (!CONFIG(SOC_INTEL_CRASHLOG)) { + printk(BIOS_DEBUG, "Crashlog is disabled, Skipping it.\n"); + return false; + } + + if (!discover_crashlog()) { + printk(BIOS_DEBUG, "Crashlog discovery result: crashlog not found\n"); + return false; + } + + collect_pmc_and_cpu_crashlog_from_srams(); + + /* Size of valid collected data can differ size in dicovery tables */ + u32 crashlog_size = crashlog_get_total_data_size(); + + return (crashlog_size > 0); +} diff --git a/src/soc/intel/tigerlake/crashlog_lib.c b/src/soc/intel/tigerlake/crashlog_lib.c new file mode 100644 index 0000000..06784f7 --- /dev/null +++ b/src/soc/intel/tigerlake/crashlog_lib.c @@ -0,0 +1,657 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <console/console.h> +#include <cbmem.h> +#include <device/pci_ops.h> +#include <device/pci_def.h> +#include <device/mmio.h> +#include <delay.h> +#include <string.h> +#include <soc/crashlog_lib.h> +#include <intelblocks/pmc_ipc.h> +#include <arch/bert_storage.h> +#include <soc/crashlog_def.h> +#include <soc/iomap.h> +#include <soc/pci_devs.h> + +/* global crashLog info */ +static bool m_pmc_crashLog_support; +static bool m_pmc_crashLog_present; +static bool m_cpu_crashLog_support; +static bool m_cpu_crashLog_present; +static u32 m_pmc_crashLog_size; +static u32 m_cpu_crashLog_size; +static u32 cpu_crash_version; +static bool clear_pmc_sram = true; + +static pmc_ipc_discovery_buf_t discovery_buf; +static pmc_crashlog_desc_table_t descriptor_table; +static tel_crashlog_devsc_cap_t cpu_cl_devsc_cap; +static cpu_crashlog_discovery_table_t cpu_cl_disc_tab; + + +int pmc_cl_get_descriptor_table(u32 desc_table_addr) +{ + int total_data_size = 0; + descriptor_table.numb_regions = read32((u32 *)desc_table_addr); + printk(BIOS_DEBUG, "CL PMC desc table: numb of regions is 0x%x at addr 0x%x\n", + descriptor_table.numb_regions, desc_table_addr); + for (int i = 0; i < descriptor_table.numb_regions; i++) { + desc_table_addr += 4; + descriptor_table.regions[i].data = read32((u32 *)(desc_table_addr)); + total_data_size += descriptor_table.regions[i].bits.size * sizeof(u32); + printk(BIOS_DEBUG, "CL PMC desc table: region 0x%x has size 0x%x at offset 0x%x\n", + i, descriptor_table.regions[i].bits.size, + descriptor_table.regions[i].bits.offset); + if (i > 255) { + printk(BIOS_ERR, "More than 255 regions in PMC crashLog descriptor tale"); + break; + } + } + return total_data_size; +} + + +bool pmc_cl_discovery(void) +{ + + u32 tmp_bar_addr = 0, desc_table_addr = 0; + + const struct pmc_ipc_buffer *req = { 0 }; + struct pmc_ipc_buffer *res = NULL; + uint32_t cmd_reg; + int r; + + cmd_reg = pmc_make_ipc_cmd(PMC_IPC_CMD_CRASHLOG, + PMC_IPC_CMD_ID_CRASHLOG_DISCOVERY, + PMC_IPC_CMD_SIZE_SHIFT); + printk(BIOS_DEBUG, "cmd_reg from pmc_make_ipc_cmd %d .\n", cmd_reg); + + r = pmc_send_ipc_cmd(cmd_reg, req, res); + + if (r < 0) { + printk(BIOS_ERR, "pmc_send_ipc_cmd failed in %s\n",__func__); + return false; + } + discovery_buf.val_64_bits = ((u64)res->buf[1] << 32) | res->buf[0]; + + + if (discovery_buf.bits.supported != 1) { + printk(BIOS_DEBUG, "PCH crashlog feature not supported .\n"); + m_pmc_crashLog_support = false; + return false; + } + m_pmc_crashLog_support = true; + + /* Program BAR 0 and enable command register memory space decoding */ + tmp_bar_addr = SPI_BASE_ADDRESS; + pci_write_config32(PCH_DEV_SRAM, PCI_BASE_ADDRESS_0, tmp_bar_addr); + pci_or_config16(PCH_DEV_SRAM, PCI_COMMAND, PCI_COMMAND_MEMORY); + + if (discovery_buf.bits.discov_mechanism == 1) { + /* discovery mode */ + if (discovery_buf.bits.base_offset & BIT_31_SET) { + printk(BIOS_DEBUG, "PCH discovery to be used is disabled .\n"); + m_pmc_crashLog_present = false; + m_pmc_crashLog_size = 0; + return false; + } + desc_table_addr = tmp_bar_addr + discovery_buf.bits.desc_tabl_offset; + m_pmc_crashLog_size = pmc_cl_get_descriptor_table(desc_table_addr); + printk(BIOS_DEBUG, "PMC crashLog size in discovery mode : 0x%X .\n", + m_pmc_crashLog_size); + } else { + /* legacy mode */ + if (discovery_buf.bits.dis) { + printk(BIOS_DEBUG, "PCH crashlog is disabled in legacy mode.\n"); + m_pmc_crashLog_present = false; + return false; + } + m_pmc_crashLog_size = (discovery_buf.bits.size != 0) ? + (discovery_buf.bits.size * sizeof(u32)) : 0xC00; + printk(BIOS_DEBUG, "PMC crashlog size in legacy mode = 0x%x .\n", + m_pmc_crashLog_size); + } + m_pmc_crashLog_present = true; + + return true; +} + + +int pmc_cl_disable(void) +{ + + const struct pmc_ipc_buffer *req = { 0 }; + struct pmc_ipc_buffer *res = NULL; + uint32_t cmd_reg; + int r; + + cmd_reg = pmc_make_ipc_cmd(PMC_IPC_CMD_CRASHLOG, + PMC_IPC_CMD_ID_CRASHLOG_DISABLE, + PMC_IPC_CMD_SIZE_SHIFT); + + r = pmc_send_ipc_cmd(cmd_reg, req, res); + + if (r < 0) { + printk(BIOS_ERR, "pmc_send_ipc_cmd failed in %s\n", __func__); + return 0; + } + + return r; +} + +int pmc_cl_re_arm_after_reset(void) +{ + + const struct pmc_ipc_buffer *req = { 0 }; + struct pmc_ipc_buffer *res = NULL; + uint32_t cmd_reg; + int r; + cmd_reg = pmc_make_ipc_cmd(PMC_IPC_CMD_CRASHLOG, + PMC_IPC_CMD_ID_CRASHLOG_RE_ARM_ON_RESET, + PMC_IPC_CMD_SIZE_SHIFT); + + r = pmc_send_ipc_cmd(cmd_reg, req, res); + + if (r < 0) { + printk(BIOS_ERR, "pmc_send_ipc_cmd failed in %s\n", __func__); + return 0; + } + + return r; +} + + +/* Sends PMC IPC to clear CrashLog from PMC SSRAM area */ +int pmc_cl_clear(void) +{ + const struct pmc_ipc_buffer *req = { 0 }; + struct pmc_ipc_buffer *res = NULL; + uint32_t cmd_reg; + int r; + + cmd_reg = pmc_make_ipc_cmd(PMC_IPC_CMD_CRASHLOG, + PMC_IPC_CMD_ID_CRASHLOG_ERASE, + PMC_IPC_CMD_SIZE_SHIFT); + + r = pmc_send_ipc_cmd(cmd_reg, req, res); + + if (r < 0) { + printk(BIOS_ERR, "pmc_send_ipc_cmd failed in %s\n", __func__); + return 0; + } + + return r; +} + +/* + * Sends PMC IPC to populate CrashLog on all reboot. + * The SSRAM area will be cleared on G3 by PMC automatically + */ + +int pmc_cl_en_gen_on_all_reboot(void) +{ + const struct pmc_ipc_buffer *req = { 0 }; + struct pmc_ipc_buffer *res = NULL; + uint32_t cmd_reg; + int r; + + cmd_reg = pmc_make_ipc_cmd(PMC_IPC_CMD_CRASHLOG, + PMC_IPC_CMD_ID_CRASHLOG_ON_RESET, + PMC_IPC_CMD_SIZE_SHIFT); + + r = pmc_send_ipc_cmd(cmd_reg, req, res); + + if (r < 0) { + printk(BIOS_ERR, "pmc_send_ipc_cmd failed in %s\n", __func__); + return 0; + } + + return r; +} + +int cpu_cl_poll_mailbox_ready(u32 cl_mailbox_addr) +{ + cpu_crashlog_mailbox_t cl_mailbox_interface; + u16 stall_cnt = 0; + + do { + cl_mailbox_interface.data = read32((u32 *)cl_mailbox_addr); + udelay(CPU_CRASHLOG_MAILBOX_WAIT_STALL); + stall_cnt++; + } while ((cl_mailbox_interface.fields.busy == 1) + && stall_cnt < CPU_CRASHLOG_MAILBOX_WAIT_TIMEOUT); + + if ((cl_mailbox_interface.fields.busy == 1) + && (stall_cnt >= CPU_CRASHLOG_MAILBOX_WAIT_TIMEOUT)) { + printk(BIOS_ERR, "CPU crashlog mailbox timed out.\n"); + return 0; + } + + return 1; +} + +int cpu_cl_mailbox_cmd(u8 cmd, u8 param) +{ + cpu_crashlog_mailbox_t cl_mailbox_intf; + u32 cl_base_addr; + + memset(&cl_mailbox_intf, 0, sizeof(cpu_crashlog_mailbox_t)); + + cl_base_addr = cpu_cl_get_bar_addr(&cpu_cl_devsc_cap); + + cl_mailbox_intf.fields.command = cmd; + cl_mailbox_intf.fields.param = param; + cl_mailbox_intf.fields.busy = 1; + + write32((u32 *)(cl_base_addr + CRASHLOG_MAILBOX_INTF_ADDRESS), + cl_mailbox_intf.data); + + cpu_cl_poll_mailbox_ready(cl_base_addr + CRASHLOG_MAILBOX_INTF_ADDRESS); + + return 1; +} + +bool cpu_cl_get_capability(tel_crashlog_devsc_cap_t *cl_devsc_cap) +{ + cl_devsc_cap->cap_data.data = pci_read_config32(SA_DEV_TMT, + TEL_DVSEC_OFFSET + TEL_DVSEC_PCIE_CAP_ID); + if (cl_devsc_cap->cap_data.fields.pcie_cap_id != TELEMETRY_EXTENDED_CAP_ID) { + printk(BIOS_DEBUG, "Read ID for Telemetry: 0x%x differs from expected: 0x%x .\n", + cl_devsc_cap->cap_data.fields.pcie_cap_id, TELEMETRY_EXTENDED_CAP_ID); + return false; + } + + /* walk through the entries until crashLog entry */ + cl_devsc_cap->devsc_data.data_32[1] = pci_read_config32(SA_DEV_TMT, TEL_DVSEV_ID); + int new_offset = 0; + while (cl_devsc_cap->devsc_data.fields.devsc_id != CRASHLOG_DVSEC_ID) { + if (cl_devsc_cap->cap_data.fields.next_cap_offset == 0 + || cl_devsc_cap->cap_data.fields.next_cap_offset == 0xFFFF) { + printk(BIOS_DEBUG, "Read invalid pcie_cap_id value: : 0x%x .\n", + cl_devsc_cap->cap_data.fields.pcie_cap_id); + return false; + } + new_offset = cl_devsc_cap->cap_data.fields.next_cap_offset; + cl_devsc_cap->cap_data.data = pci_read_config32(SA_DEV_TMT, + new_offset + TEL_DVSEC_PCIE_CAP_ID); + cl_devsc_cap->devsc_data.data_32[1] = pci_read_config32(SA_DEV_TMT, + new_offset + TEL_DVSEV_ID); + } + cpu_crash_version = cl_devsc_cap->devsc_data.fields.devsc_ver; + + cl_devsc_cap->discovery_data.data = pci_read_config32(SA_DEV_TMT, new_offset + + TEL_DVSEV_DISCOVERY_TABLE_OFFSET); + + return true; +} + +u32 cpu_cl_get_bar_addr(tel_crashlog_devsc_cap_t *cl_devsc_cap) +{ + u32 base_addr = 0; + if (cpu_cl_devsc_cap.discovery_data.fields.t_bir_q == TEL_DVSEC_TBIR_BAR0) + base_addr = pci_read_config32(SA_DEV_TMT, TEL_CFG_BAR0) & 0xFFFFFFFFF0; + else if (cpu_cl_devsc_cap.discovery_data.fields.t_bir_q == TEL_DVSEC_TBIR_BAR1) + base_addr = pci_read_config32(SA_DEV_TMT, TEL_CFG_BAR1) & 0xFFFFFFFFF0; + else + printk(BIOS_ERR, "Invalid TEL_CFG_BAR value %d:\n", + cpu_cl_devsc_cap.discovery_data.fields.t_bir_q); + + + return base_addr; +} + +int cpu_cl_clear_data(void) +{ + return cpu_cl_mailbox_cmd(CPU_CRASHLOG_CMD_CLEAR, 0); +} + + +bool cpu_cl_get_discovery_table(void) +{ + u32 bar_addr = 0, disc_tab_addr = 0; + bar_addr = cpu_cl_get_bar_addr(&cpu_cl_devsc_cap); + disc_tab_addr = bar_addr + + cpu_cl_devsc_cap.discovery_data.fields.discovery_table_offset; + memset(&cpu_cl_disc_tab, 0, sizeof(cpu_crashlog_discovery_table_t)); + + cpu_cl_disc_tab.header.data = ((u64)read32((u32 *)disc_tab_addr) + + ((u64)read32((u32 *)(disc_tab_addr + 4)) << 32)); + + cpu_cl_disc_tab.cmd_mailbox.data = read32((u32 *)(disc_tab_addr + 8)); + cpu_cl_disc_tab.mailbox_data = read32((u32 *)(disc_tab_addr + 12)); + + printk(BIOS_DEBUG, "cpu_crashlog_discovery_table buffer count: 0x%x\n", + cpu_cl_disc_tab.header.fields.count); + + if (cpu_cl_disc_tab.header.fields.guid != CPU_CRASHLOG_DISC_TAB_GUID_VALID) { + printk(BIOS_ERR, "Invalid CPU crashlog discovery table GUID, expected = 0x%X ," + "actual = 0x%X\n", CPU_CRASHLOG_DISC_TAB_GUID_VALID, + cpu_cl_disc_tab.header.fields.guid); + return false; + } + + int cur_offset = 0; + for (int i = 0; i < cpu_cl_disc_tab.header.fields.count ; i++) { + cur_offset = 16 + 8*i; + cpu_cl_disc_tab.buffers[i].data = ((u64)read32((u32 *)(disc_tab_addr + + cur_offset)) + ((u64)read32((u32 *) + (disc_tab_addr + cur_offset + 4)) << 32)); + printk(BIOS_DEBUG, "cpu_crashlog_discovery_table buffer: 0x%x size:" + "0x%x offset: 0x%x\n", i, cpu_cl_disc_tab.buffers[i].fields.size, + cpu_cl_disc_tab.buffers[i].fields.offset); + m_cpu_crashLog_size += cpu_cl_disc_tab.buffers[i].fields.size * sizeof(u32); + } + + m_cpu_crashLog_present = m_cpu_crashLog_size > 0; + + return true; +} + +bool cpu_cl_discovery(void) +{ + memset(&cpu_cl_devsc_cap, 0, sizeof(tel_crashlog_devsc_cap_t)); + + if (!cpu_cl_get_capability(&cpu_cl_devsc_cap)) { + printk(BIOS_ERR, "CPU crashlog capability not found.\n"); + m_cpu_crashLog_support = false; + return false; + } + + m_cpu_crashLog_support = true; + + /* Program BAR address and enable command register memory space decoding */ + u32 tmp_bar_addr = PCH_PWRM_BASE_ADDRESS; + printk(BIOS_DEBUG, "tmp_bar_addr: 0x%X .\n", tmp_bar_addr); + + if (cpu_cl_devsc_cap.discovery_data.fields.t_bir_q == TEL_DVSEC_TBIR_BAR0) { + pci_write_config32(SA_DEV_TMT, TEL_CFG_BAR0, tmp_bar_addr); + } else if (cpu_cl_devsc_cap.discovery_data.fields.t_bir_q == TEL_DVSEC_TBIR_BAR1) { + pci_write_config32(SA_DEV_TMT, TEL_CFG_BAR1, tmp_bar_addr); + } else { + printk(BIOS_DEBUG, "invalid discovery data t_bir_q: 0x%x\n", + cpu_cl_devsc_cap.discovery_data.fields.t_bir_q); + return false; + } + pci_or_config16(SA_DEV_TMT, PCI_COMMAND, PCI_COMMAND_MEMORY); + + if (!cpu_cl_get_discovery_table()) { + printk(BIOS_ERR, "CPU crashlog discovery table not valid.\n"); + m_cpu_crashLog_present = false; + return false; + } + m_cpu_crashLog_present = true; + + return true; +} + + +bool discover_crashlog(void) +{ + bool cpu_cl_discovered = false, pmc_cl_discovered = false; + + memset(&discovery_buf, 0, sizeof(pmc_ipc_discovery_buf_t)); + memset(&descriptor_table, 0, sizeof(pmc_crashlog_desc_table_t)); + memset(&cpu_cl_devsc_cap, 0, sizeof(tel_crashlog_devsc_cap_t)); + + /* PCH crashLog discovery */ + pmc_cl_discovered = pmc_cl_discovery(); + + /* CPU crashLog discovery */ + cpu_cl_discovered = cpu_cl_discovery(); + + return (cpu_cl_discovered || pmc_cl_discovered); +} + +int crashlog_get_total_data_size(void) +{ + return m_pmc_crashLog_size + m_cpu_crashLog_size; +} + + +bool cl_copy_data_from_sram(u32 src_bar, + u32 offset, + u32 size, + u32 *dest_addr, + u32 buffer_index, + bool pmc_sram) +{ + if (src_bar == 0) { + printk(BIOS_ERR, "Invalid bar 0x%x and offset 0x%x for %s .\n", + src_bar, offset, __func__); + return false; + } + + u32 src_addr = src_bar + offset; + + u32 data = read32((u32 *)src_addr); + /*PMC: copy if 1st DWORD in buffer is not zero and its 31st bit is not set */ + if (pmc_sram && !(data && !(data & BIT_31_SET))) { + printk(BIOS_DEBUG, "Invalid data 0x%x at offset 0x%x from addr 0x%x" + " of PMC SRAM.\n", data, offset, src_bar); + return false; + } + /*CPU: don't copy if 1st DWORD in first buffer is zero */ + if (!pmc_sram && !data && (buffer_index == 0)) { + printk(BIOS_DEBUG, "Invalid data 0x%x at offset 0x%x from addr 0x%x" + " of telemetry SRAM.\n", data, offset, src_bar); + return false; + } + + u32 copied = 0; + while (copied < size) { + /* DW by DW copy: byte access to PMC SRAM not allowed */ + *dest_addr = read32((u32 *)src_addr); + dest_addr++; + src_addr += 4; + copied++; + } + return true; +} + +void pmc_cl_get_sram_data(void) +{ + u32 *dest = NULL; + u32 tmp_bar_addr = SPI_BASE_ADDRESS; + + /*PMC SSRAM MMIO access */ + if (pci_read_config16(PCH_DEV_SRAM, PCI_VENDOR_ID) == 0xFFFF) { + printk(BIOS_ERR, "PMC SSRAM PCI device is disabled.\n"); + return; + } + + if (discovery_buf.bits.supported != 1) { + printk(BIOS_DEBUG, "PCH crashlog feature not supported.\n"); + goto pmc_send_re_arm_after_reset; + } + + /* Get the size of data to copy */ + if (discovery_buf.bits.discov_mechanism == 1) { + if (discovery_buf.bits.base_offset & BIT_31_SET) { + printk(BIOS_DEBUG, "PCH discovery to be used is disabled.\n"); + goto pmc_send_re_arm_after_reset; + } + printk(BIOS_DEBUG, "PMC crashLog size in discovery mode : 0x%X\n", + m_pmc_crashLog_size); + } else { + if (discovery_buf.bits.dis) { + printk(BIOS_DEBUG, "PCH crashlog is disabled in legacy mode.\n"); + return; + } + m_pmc_crashLog_size = (discovery_buf.bits.size != 0) ? + discovery_buf.bits.size : 0xC00; + printk(BIOS_DEBUG, "PMC crashLog size in legacy mode : 0x%X\n", + m_pmc_crashLog_size); + } + + /* allocate mem for the record to be copied */ + unsigned long pmc_cl_cbmem_addr; + + pmc_cl_cbmem_addr = (unsigned long) cbmem_add(CBMEM_ID_PMC_CRASHLOG, + m_pmc_crashLog_size); + if (!pmc_cl_cbmem_addr) { + printk(BIOS_ERR, "Unable to allocate CBMEM PMC crashLog entry.\n"); + return; + } + memset((void *)pmc_cl_cbmem_addr, 0, m_pmc_crashLog_size); + dest = (u32 *)(uintptr_t) pmc_cl_cbmem_addr; + bool pmc_sram = true; + if (discovery_buf.bits.discov_mechanism == 1) { + for (int i = 0; i < descriptor_table.numb_regions; i++) { + if (cl_copy_data_from_sram(tmp_bar_addr, + descriptor_table.regions[i].bits.offset, + descriptor_table.regions[i].bits.size, + dest, + i, + pmc_sram)) { + dest = (u32 *)((u32)dest + + (descriptor_table.regions[i].bits.size + * sizeof(u32))); + } else { + m_pmc_crashLog_size -= descriptor_table.regions[i].bits.size * + sizeof(u32); + printk(BIOS_DEBUG, "discover mode PMC crashlog size adjusted" + " to: 0x%x\n", m_pmc_crashLog_size); + } + } + } else { + if (!cl_copy_data_from_sram(tmp_bar_addr, + discovery_buf.bits.base_offset, + discovery_buf.bits.size, + dest, + 0, + pmc_sram)) { + m_pmc_crashLog_size -= discovery_buf.bits.size * sizeof(u32); + printk(BIOS_DEBUG, "legacy mode PMC crashlog size adjusted to: 0x%x\n", + m_pmc_crashLog_size); + } + } + +pmc_send_re_arm_after_reset: + /* when bit 7 of discov cmd resp is set -> bit 2 of size field */ + if (discovery_buf.bits.size & BIT_2_SET) + pmc_cl_re_arm_after_reset(); + + /* Clear the SSRAM region after copying the error log */ + if (clear_pmc_sram) + pmc_cl_clear(); + +} + +void cpu_cl_get_telemtry_sram_data(void) +{ + u32 tmp_bar_addr = 0; + u32 *dest = NULL; + + if (m_cpu_crashLog_size < 1) { + printk(BIOS_DEBUG, "%s: no data to collect .\n", __func__); + return; + } + + printk(BIOS_DEBUG, "CPU crash data size: 0x%X bytes in 0x%X region(s) .\n", + m_cpu_crashLog_size, cpu_cl_disc_tab.header.fields.count); + + /* allocate memory buffers for CPU crashog data to be copied */ + unsigned long cpu_crashlog_cbmem_addr; + cpu_crashlog_cbmem_addr = (unsigned long) cbmem_add(CBMEM_ID_CPU_CRASHLOG, + m_cpu_crashLog_size); + if (!cpu_crashlog_cbmem_addr) { + printk(BIOS_ERR, "Failed to add CPU main crashLog entries to CBMEM.\n"); + return; + } + + memset((void *) cpu_crashlog_cbmem_addr, 0, m_cpu_crashLog_size); + tmp_bar_addr = cpu_cl_get_bar_addr(&cpu_cl_devsc_cap); + dest = (u32 *)(uintptr_t) cpu_crashlog_cbmem_addr; + bool pmc_sram = false; + cpu_crashlog_buffer_info_t buff_info; + + for (int i = 0 ; i < cpu_cl_disc_tab.header.fields.count ; i++) { + buff_info = cpu_cl_disc_tab.buffers[i]; + + if (cl_copy_data_from_sram(tmp_bar_addr, + cpu_cl_disc_tab.buffers[i].fields.offset, + cpu_cl_disc_tab.buffers[i].fields.size, + dest, + i, + pmc_sram)) { + dest = (u32 *)((u32)dest + + (cpu_cl_disc_tab.buffers[i].fields.size * sizeof(u32))); + } else { + m_cpu_crashLog_size -= cpu_cl_disc_tab.buffers[i].fields.size + * sizeof(u32); + + /* for CPU skip all buffers if the 1st one is not valid */ + if (i == 0) { + m_cpu_crashLog_size = 0; + break; + } + } + } + + /* clear telemetry SRAM region */ + cpu_cl_clear_data(); + +} + +void collect_pmc_and_cpu_crashlog_from_srams(void) +{ + if (m_pmc_crashLog_support && m_pmc_crashLog_present) { + pmc_cl_en_gen_on_all_reboot(); + printk(BIOS_DEBUG, "Crashlog collection enabled on every reboot.\n"); + pmc_cl_get_sram_data(); + } else { + printk(BIOS_DEBUG, "Skipping PMC crashLog collection. Data not present.\n"); + } + + printk(BIOS_DEBUG, "m_cpu_crashLog_size : 0x%X bytes\n", m_cpu_crashLog_size); + if (m_cpu_crashLog_support && m_cpu_crashLog_present && (m_cpu_crashLog_size > 0)) { + printk(BIOS_DEBUG, "CPU crashLog present.\n"); + cpu_cl_get_telemtry_sram_data(); + + } else { + printk(BIOS_DEBUG, "Skipping CPU crashLog collection. Data not present.\n"); + } +} + +int crashlog_get_cpu_record_size(void) +{ + return m_cpu_crashLog_size; +} + +int crashlog_get_pmc_record_size(void) +{ + return m_pmc_crashLog_size; +} + +bool crashlog_fill_cpu_records(void *cl_record) +{ + void *cl_src_addr = NULL; + + if (!m_cpu_crashLog_present || m_cpu_crashLog_size == 0) { + printk(BIOS_DEBUG, "CPU crashLog not present, skipping.\n"); + return false; + } + + printk(BIOS_DEBUG, "CPU crash data collection.\n"); + cl_src_addr = cbmem_find(CBMEM_ID_CPU_CRASHLOG); + memcpy(cl_record, cl_src_addr, m_cpu_crashLog_size); + + return true; +} + +bool crashlog_fill_pmc_records(void *cl_record) +{ + void *cl_src_addr = NULL; + + if (!m_pmc_crashLog_present || m_pmc_crashLog_size == 0) { + printk(BIOS_DEBUG, "PMC crashLog not present, skipping.\n"); + return false; + } + + printk(BIOS_DEBUG, "PMC crash data collection.\n"); + cl_src_addr = cbmem_find(CBMEM_ID_PMC_CRASHLOG); + memcpy(cl_record, cl_src_addr, m_pmc_crashLog_size); + + return true; +} diff --git a/src/soc/intel/tigerlake/include/soc/crashlog_def.h b/src/soc/intel/tigerlake/include/soc/crashlog_def.h new file mode 100644 index 0000000..0f586ef --- /dev/null +++ b/src/soc/intel/tigerlake/include/soc/crashlog_def.h @@ -0,0 +1,56 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * This file is part of the coreboot project. + * + * Copyright 2021 Intel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hop that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. +*/ + +#ifndef _SOC_CRASHLOG_DEF_H_ +#define _SOC_CRASHLOG_DEF_H_ + +/* PMC CrashLog Command */ +#define PMC_IPC_CMD_CRASHLOG 0xA6 +#define PMC_IPC_CMD_ID_CRASHLOG_DISCOVERY 0x01 +#define PMC_IPC_CMD_ID_CRASHLOG_DISABLE 0x02 +#define PMC_IPC_CMD_ID_CRASHLOG_ERASE 0x04 +#define PMC_IPC_CMD_ID_CRASHLOG_ON_RESET 0x05 +#define PMC_IPC_CMD_ID_CRASHLOG_RE_ARM_ON_RESET 0x06 +#define BIT_2_SET 0x04 +#define BIT_31_SET 0x80000000 + +/* DVSEC capability Registers */ +#define TEL_DVSEC_OFFSET 0x100 +#define TEL_DVSEC_PCIE_CAP_ID 0x0 +#define TEL_DVSEC_NEXT_CAP 0x2 +#define TEL_DVSEV_ID 0x8 +#define TEL_DVSEV_DISCOVERY_TABLE_OFFSET 0xC +#define TELEMETRY_EXTENDED_CAP_ID 0x23 +#define CRASHLOG_DVSEC_ID 0x04 +#define TEL_DVSEC_TBIR_BAR0 0 +#define TEL_DVSEC_TBIR_BAR1 1 + +/* CPU CrashLog MMIO Registers */ +#define CRASHLOG_MAILBOX_INTF_ADDRESS 0x6038 +#define CRASHLOG_POINTER_SIZE_FIELD_OFFSET 0x04 + +/* CPU CrashLog Mailbox commands */ +#define CPU_CRASHLOG_CMD_DISABLE 0 +#define CPU_CRASHLOG_CMD_CLEAR 2 +#define CPU_CRASHLOG_MAILBOX_WAIT_STALL 1 +#define CPU_CRASHLOG_MAILBOX_WAIT_TIMEOUT 1000 +#define CPU_CRASHLOG_DISC_TAB_GUID_VALID 0x1600 + +#define CRASHLOG_SIZE_DEBUG_PURPOSE 0x640 + +#endif /* _SOC_CRASHLOG_DEF_H_ */ diff --git a/src/soc/intel/tigerlake/include/soc/crashlog_lib.h b/src/soc/intel/tigerlake/include/soc/crashlog_lib.h new file mode 100644 index 0000000..deeca83 --- /dev/null +++ b/src/soc/intel/tigerlake/include/soc/crashlog_lib.h @@ -0,0 +1,173 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * This file is part of the coreboot project. + * + * Copyright 2021 Intel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_COMMON_BLOCK_CRASHLOG_LIB_H_ +#define _SOC_COMMON_BLOCK_CRASHLIB_LIB_H_ + +#include <arch/io.h> +#include <acpi/acpi.h> +#include <fsp/util.h> + +/* PMC crashlog discovery structs */ +typedef union { + struct { + u16 offset; + u16 size; + } bits; + u32 data; +} __packed pmc_crashlog_discov_region_t; + +typedef struct { + u32 numb_regions; + pmc_crashlog_discov_region_t regions[256]; +} __packed pmc_crashlog_desc_table_t; + +typedef union { + struct { + u32 supported :1; + u32 dis :1; + u32 discov_mechanism :2; + u32 size :12; + u32 base_offset :16; /* Start offset of CrashLog in PMC SSRAM */ + u32 rsv :16; + u32 desc_tabl_offset :16; /* start offset of descriptor table */ + } bits; + u64 val_64_bits; +} __packed pmc_ipc_discovery_buf_t; + + +/* CPU/TELEMETRY crashlog discovery structs */ + +typedef union { + struct { + u32 pcie_cap_id :16; + u32 cap_ver :4; + u32 next_cap_offset :12; + } fields; + u32 data; +} __packed cap_data_t; + +typedef union { + struct { + u64 devsc_ven_id :16; + u64 devsc_ver :4; + u64 devsc_len :12; + u64 devsc_id :16; + u64 num_entries :8; /*Numb of telemetry aggregators in lookup table. */ + u64 entries_size :8; /* Entry Size in DWORDS */ + } fields; + u64 data_64; + u32 data_32[2]; +} __packed devsc_data_t; + +typedef union { + struct { + u32 t_bir_q :3; /* tBIR, The BAR to be used */ + u32 discovery_table_offset :29; + } fields; + u32 data; +} __packed discovery_data_t; + +typedef struct { + cap_data_t cap_data; + devsc_data_t devsc_data; + discovery_data_t discovery_data; +} __packed tel_crashlog_devsc_cap_t; + +typedef union { + struct { + u64 access_type :4; + u64 crash_type :4; + u64 count :8; + u64 reserved :16; + u64 guid :32; + } fields; + u64 data; +} __packed cpu_crashlog_header_t; + + +/* Structures for CPU CrashLog mailbox interface */ +typedef union { + struct { + u32 command :8; + u32 param :8; + u32 reserved :15; + u32 busy :1; + } fields; + u32 data; +} __packed cpu_crashlog_mailbox_t; + +typedef union { + struct { + u32 offset :32; + u32 size :16; + u32 reserved :16; + } fields; + u64 data; +} __packed cpu_crashlog_buffer_info_t; + +typedef struct { + cpu_crashlog_header_t header; + cpu_crashlog_mailbox_t cmd_mailbox; + u32 mailbox_data; + cpu_crashlog_buffer_info_t buffers[256]; +} __packed cpu_crashlog_discovery_table_t; + + +static const EFI_GUID FW_ERR_SECTION_GUID = { + 0x81212a96, 0x09ed, 0x4996, + { 0x94, 0x71, 0x8d, 0x72, 0x9c, 0x8e, 0x69, 0xed } +}; + +int pmc_cl_get_descriptor_table(u32 desc_table_addr); +bool pmc_cl_discovery(void); +int pmc_cl_disable(void); +int pmc_cl_clear(void); +int pmc_cl_re_arm_after_reset(void); +int pmc_cl_en_gen_on_all_reboot(void); +void pmc_cl_get_sram_data(void); + +bool discover_crashlog(void); +int crashlog_get_total_data_size(void); +bool cl_copy_data_from_sram(u32 src_bar, + u32 offset, + u32 size, + u32 *dest_addr, + u32 buffer_index, + bool pmc_sram); + +int cpu_cl_poll_mailbox_ready(u32 cl_mailbox_addr); +int cpu_cl_mailbox_cmd(u8 cmd, u8 param); +bool cpu_cl_get_capability(tel_crashlog_devsc_cap_t *cl_devsc_cap); +u32 cpu_cl_get_bar_addr(tel_crashlog_devsc_cap_t *cl_devsc_cap); +int cpu_cl_clear_data(void); +void cpu_cl_get_header(u32 base_addr, + cpu_crashlog_header_t *cl_header_buff); +bool cpu_cl_disable(void); +bool cpu_cl_get_discovery_table(void); +bool cpu_cl_discovery(void); + +void cpu_cl_get_telemtry_sram_data(void); +void collect_pmc_and_cpu_crashlog_from_srams(void); + +int crashlog_get_cpu_record_size(void); +int crashlog_get_pmc_record_size(void); +bool crashlog_fill_cpu_records(void *cl_record); +bool crashlog_fill_pmc_records(void *cl_record); + +#endif /* _SOC_COMMON_BLOCK_CRASHLOG_LIB_H_ */ diff --git a/src/soc/intel/tigerlake/include/soc/iomap.h b/src/soc/intel/tigerlake/include/soc/iomap.h index 6fa29d3..47d2551 100644 --- a/src/soc/intel/tigerlake/include/soc/iomap.h +++ b/src/soc/intel/tigerlake/include/soc/iomap.h @@ -102,4 +102,8 @@ #define P2SB_BAR CONFIG_PCR_BASE_ADDRESS #define P2SB_SIZE (16 * MiB)
+/* PCI Configuration Space Registers for telemetry */ +#define TEL_CFG_BAR0 0x10 +#define TEL_CFG_BAR1 0x14 + #endif diff --git a/src/soc/intel/tigerlake/include/soc/pci_devs.h b/src/soc/intel/tigerlake/include/soc/pci_devs.h index ac0498f..4737fc7 100644 --- a/src/soc/intel/tigerlake/include/soc/pci_devs.h +++ b/src/soc/intel/tigerlake/include/soc/pci_devs.h @@ -5,21 +5,24 @@
#include <device/pci_def.h>
+#define _SA_DEVFN(slot) PCI_DEVFN(SA_DEV_SLOT_ ## slot, 0) #define _PCH_DEVFN(slot, func) PCI_DEVFN(PCH_DEV_SLOT_ ## slot, func)
#if !defined(__SIMPLE_DEVICE__) #include <device/device.h> +#define _SA_DEV(slot) pcidev_path_on_root(_SA_DEVFN(slot)) #define _PCH_DEV(slot, func) pcidev_path_on_root_debug(_PCH_DEVFN(slot, func), __func__) #else +#define _SA_DEV(slot) PCI_DEV(0, SA_DEV_SLOT_ ## slot, 0) #define _PCH_DEV(slot, func) PCI_DEV(0, PCH_DEV_SLOT_ ## slot, func) #endif
/* System Agent Devices */
#define SA_DEV_SLOT_ROOT 0x00 -#define SA_DEVFN_ROOT PCI_DEVFN(SA_DEV_SLOT_ROOT, 0) +#define SA_DEVFN_ROOT PCI_DEVFN(SA_DEV_SLOT_ROOT, 0) #if defined(__SIMPLE_DEVICE__) -#define SA_DEV_ROOT PCI_DEV(0, SA_DEV_SLOT_ROOT, 0) +#define SA_DEV_ROOT PCI_DEV(0, SA_DEV_SLOT_ROOT, 0) #endif
#define SA_DEV_SLOT_IGD 0x02 @@ -49,6 +52,10 @@ #define SA_DEV_TBT2 PCI_DEV(0, SA_DEV_SLOT_TBT, 2) #define SA_DEV_TBT3 PCI_DEV(0, SA_DEV_SLOT_TBT, 3)
+#define SA_DEV_SLOT_TMT 0x0A +#define SA_DEVFN_TMT _SA_DEVFN(TMT) +#define SA_DEV_TMT _SA_DEV(TMT) + #define SA_DEV_SLOT_TCSS 0x0d #define NUM_TCSS_DMA_FUNCTIONS 2 #define SA_DEVFN_TCSS_DMA(x) PCI_DEVFN(SA_DEV_SLOT_TCSS, ((x) + 2)) diff --git a/src/soc/intel/tigerlake/romstage/fsp_params.c b/src/soc/intel/tigerlake/romstage/fsp_params.c index 27630ec..ebcc7d4 100644 --- a/src/soc/intel/tigerlake/romstage/fsp_params.c +++ b/src/soc/intel/tigerlake/romstage/fsp_params.c @@ -215,6 +215,12 @@
/* Change TmeEnable UPD value according to INTEL_TME Kconfig */ m_cfg->TmeEnable = CONFIG(INTEL_TME); + + /* crashLog config */ + if (CONFIG(SOC_INTEL_CRASHLOG)) { + m_cfg->CpuCrashLogDevice = 1; + m_cfg->CpuCrashLogEnable = 1; + } }
void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) diff --git a/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h index 35cc43b..1b3c859 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h @@ -72,9 +72,11 @@ **/ UINT8 EnableAbove4GBMmio;
-/** Offset 0x004B - Reserved +/** Offset 0x004B - Enable/Disable CrashLog Device 10 + Enable(Default): Enable CPU CrashLog Device 10, Disable: Disable CPU CrashLog + $EN_DIS **/ - UINT8 Reserved0; + UINT8 CpuCrashLogDevice;
/** Offset 0x004C - MemorySpdPtr00 **/
-
Francois Toguo Fotso (Code Review)