Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/80193?usp=email )
Change subject: soc/intel: Use write{64,32,16,8}p and read{64,32,16,8}p ......................................................................
soc/intel: Use write{64,32,16,8}p and read{64,32,16,8}p
Change-Id: I4022e3bbfacf35d0529e46dc82cf303dae9438e4 Signed-off-by: Elyes Haouas ehaouas@noos.fr --- M src/soc/intel/braswell/gpio.c M src/soc/intel/braswell/lpc_init.c M src/soc/intel/braswell/lpe.c M src/soc/intel/braswell/southcluster.c M src/soc/intel/denverton_ns/acpi.c M src/soc/intel/denverton_ns/bootblock/uart.c M src/soc/intel/denverton_ns/gpio_dnv.c M src/soc/intel/denverton_ns/lpc.c M src/soc/intel/denverton_ns/romstage.c M src/soc/intel/denverton_ns/sata.c M src/soc/intel/meteorlake/crashlog.c M src/soc/intel/xeon_sp/spr/soc_acpi.c 12 files changed, 72 insertions(+), 70 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/80193/1
diff --git a/src/soc/intel/braswell/gpio.c b/src/soc/intel/braswell/gpio.c index 58970e83..ec2a54c 100644 --- a/src/soc/intel/braswell/gpio.c +++ b/src/soc/intel/braswell/gpio.c @@ -204,8 +204,8 @@ community->gpio_to_pad[gpio], gpio); #endif /* Write pad configurations to conf0 and conf1 register */ - write32((void *)(reg + PAD_CONF0_REG), config->pad_conf0); - write32((void *)(reg + PAD_CONF1_REG), config->pad_conf1); + write32p((reg + PAD_CONF0_REG), config->pad_conf0); + write32p((reg + PAD_CONF1_REG), config->pad_conf1); } }
@@ -215,14 +215,14 @@ #endif
/* Wake */ - write32((void *)(community->pad_base + GPIO_WAKE_MASK_REG0), gpio_wake0); + write32p((community->pad_base + GPIO_WAKE_MASK_REG0), gpio_wake0);
/* Wake mask config for communities with 2 regs */ if (community->gpio_count > 32) - write32((void *)(community->pad_base + GPIO_WAKE_MASK_REG1), gpio_wake1); + write32p((community->pad_base + GPIO_WAKE_MASK_REG1), gpio_wake1);
/* Interrupt */ - write32((void *)(community->pad_base + GPIO_INTERRUPT_MASK), gpio_int_mask); + write32p((community->pad_base + GPIO_INTERRUPT_MASK), gpio_int_mask); }
void setup_soc_gpios(struct soc_gpio_config *config, u8 enable_xdp_tap) @@ -233,7 +233,7 @@ * Write the default value 0xffffff to the SW write_access_policy_interrupt_reg * to allow the SW interrupt mask register to be set */ - write32((void *)(COMMUNITY_GPSOUTHWEST_BASE + 0x108), 0xffffffff); + write32p((COMMUNITY_GPSOUTHWEST_BASE + 0x108), 0xffffffff);
printk(BIOS_DEBUG, "north\n"); setup_gpios(config->north, &gpnorth_community); diff --git a/src/soc/intel/braswell/lpc_init.c b/src/soc/intel/braswell/lpc_init.c index d476d5d..15a17b7 100644 --- a/src/soc/intel/braswell/lpc_init.c +++ b/src/soc/intel/braswell/lpc_init.c @@ -37,41 +37,41 @@ static void lpc_gpio_config(u32 cycle) { if (cycle == SUSPEND_CYCLE) { /* Suspend cycle */ - write32((void *)(COMMUNITY_GPSOUTHEAST_BASE + LPC_FRAME_MMIO_OFFSET), + write32p((COMMUNITY_GPSOUTHEAST_BASE + LPC_FRAME_MMIO_OFFSET), PAD_CFG0_NATIVE_PU20K(1));
- write32((void *)(COMMUNITY_GPSOUTHEAST_BASE + LPC_AD0_MMIO_OFFSET), + write32p((COMMUNITY_GPSOUTHEAST_BASE + LPC_AD0_MMIO_OFFSET), PAD_CFG0_NATIVE_PU20K(1));
- write32((void *)(COMMUNITY_GPSOUTHEAST_BASE + LPC_AD1_MMIO_OFFSET), + write32p((COMMUNITY_GPSOUTHEAST_BASE + LPC_AD1_MMIO_OFFSET), PAD_CFG0_NATIVE_PU20K(1));
- write32((void *)(COMMUNITY_GPSOUTHEAST_BASE + LPC_AD2_MMIO_OFFSET), + write32p((COMMUNITY_GPSOUTHEAST_BASE + LPC_AD2_MMIO_OFFSET), PAD_CFG0_NATIVE_PU20K(1));
- write32((void *)(COMMUNITY_GPSOUTHEAST_BASE + LPC_AD3_MMIO_OFFSET), + write32p((COMMUNITY_GPSOUTHEAST_BASE + LPC_AD3_MMIO_OFFSET), PAD_CFG0_NATIVE_PU20K(1));
- write32((void *)(COMMUNITY_GPSOUTHEAST_BASE + LPC_CLKRUN_MMIO_OFFSET), + write32p((COMMUNITY_GPSOUTHEAST_BASE + LPC_CLKRUN_MMIO_OFFSET), PAD_CFG0_NATIVE_PD20K(1));
} else { /* Resume cycle */ - write32((void *)(COMMUNITY_GPSOUTHEAST_BASE + LPC_FRAME_MMIO_OFFSET), + write32p((COMMUNITY_GPSOUTHEAST_BASE + LPC_FRAME_MMIO_OFFSET), PAD_CFG0_NATIVE_M1);
- write32((void *)(COMMUNITY_GPSOUTHEAST_BASE + LPC_AD0_MMIO_OFFSET), + write32p((COMMUNITY_GPSOUTHEAST_BASE + LPC_AD0_MMIO_OFFSET), PAD_CFG0_NATIVE_PU20K(1));
- write32((void *)(COMMUNITY_GPSOUTHEAST_BASE + LPC_AD1_MMIO_OFFSET), + write32p((COMMUNITY_GPSOUTHEAST_BASE + LPC_AD1_MMIO_OFFSET), PAD_CFG0_NATIVE_PU20K(1));
- write32((void *)(COMMUNITY_GPSOUTHEAST_BASE + LPC_AD2_MMIO_OFFSET), + write32p((COMMUNITY_GPSOUTHEAST_BASE + LPC_AD2_MMIO_OFFSET), PAD_CFG0_NATIVE_PU20K(1));
- write32((void *)(COMMUNITY_GPSOUTHEAST_BASE + LPC_AD3_MMIO_OFFSET), + write32p((COMMUNITY_GPSOUTHEAST_BASE + LPC_AD3_MMIO_OFFSET), PAD_CFG0_NATIVE_PU20K(1));
- write32((void *)(COMMUNITY_GPSOUTHEAST_BASE + LPC_CLKRUN_MMIO_OFFSET), + write32p((COMMUNITY_GPSOUTHEAST_BASE + LPC_CLKRUN_MMIO_OFFSET), PAD_CFG0_NATIVE_M1); } } diff --git a/src/soc/intel/braswell/lpe.c b/src/soc/intel/braswell/lpe.c index 92632d8..d776c6a 100644 --- a/src/soc/intel/braswell/lpe.c +++ b/src/soc/intel/braswell/lpe.c @@ -122,8 +122,8 @@
/* Also put the address in MMIO space like on C0 BTM */ mmio = find_resource(dev, PCI_BASE_ADDRESS_0); - write32((void *)(uintptr_t)(mmio->base + FIRMWARE_REG_BASE_C0), res->base); - write32((void *)(uintptr_t)(mmio->base + FIRMWARE_REG_LENGTH_C0), res->size); + write32p((uintptr_t)(mmio->base + FIRMWARE_REG_BASE_C0), res->base); + write32p((uintptr_t)(mmio->base + FIRMWARE_REG_LENGTH_C0), res->size); }
static void lpe_init(struct device *dev) diff --git a/src/soc/intel/braswell/southcluster.c b/src/soc/intel/braswell/southcluster.c index a0df97c..caa62bc 100644 --- a/src/soc/intel/braswell/southcluster.c +++ b/src/soc/intel/braswell/southcluster.c @@ -248,7 +248,7 @@ PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL);
/* Use IRQ9 for SCI Interrupt */ - write32((void *)(ilb_base + ACTL), 0); + write32p((ilb_base + ACTL), 0);
isa_dma_init();
@@ -256,11 +256,11 @@
/* Set up the PIRQ PIC routing based on static config. */ for (i = 0; i < NUM_PIRQS; i++) - write8((void *)(pr_base + i*sizeof(ir->pic[i])), ir->pic[i]); + write8p((pr_base + i*sizeof(ir->pic[i])), ir->pic[i]);
/* Set up the per device PIRQ routing base on static config. */ for (i = 0; i < NUM_IR_DEVS; i++) - write16((void *)(ir_base + i*sizeof(ir->pcidev[i])), ir->pcidev[i]); + write16p((ir_base + i*sizeof(ir->pcidev[i])), ir->pcidev[i]);
/* Interrupt 9 should be level triggered (SCI) */ i8259_configure_irq_trigger(9, 1); diff --git a/src/soc/intel/denverton_ns/acpi.c b/src/soc/intel/denverton_ns/acpi.c index d0fde3e..7cabcf64 100644 --- a/src/soc/intel/denverton_ns/acpi.c +++ b/src/soc/intel/denverton_ns/acpi.c @@ -8,6 +8,7 @@ #include <cpu/cpu.h> #include <cpu/x86/smm.h> #include <string.h> +#include <device/mmio.h> #include <device/pci.h> #include <device/pci_ops.h> #include <cbmem.h> @@ -168,7 +169,7 @@ uint64_t vtbar; unsigned long tmp = current;
- vtbar = read64((void *)(DEFAULT_MCHBAR + MCH_VTBAR_OFFSET)) & MCH_VTBAR_MASK; + vtbar = read64p((DEFAULT_MCHBAR + MCH_VTBAR_OFFSET)) & MCH_VTBAR_MASK; printk(BIOS_DEBUG, "DEFVTBAR:0x%llx\n", vtbar); if (!vtbar) return current; diff --git a/src/soc/intel/denverton_ns/bootblock/uart.c b/src/soc/intel/denverton_ns/bootblock/uart.c index ea99051..c85a157 100644 --- a/src/soc/intel/denverton_ns/bootblock/uart.c +++ b/src/soc/intel/denverton_ns/bootblock/uart.c @@ -65,7 +65,7 @@ reg32 &= ~B_PCH_GPIO_PAD_MODE; reg32 |= (UINT32)(V_PCH_GPIO_PAD_MODE_NAT_1 << N_PCH_GPIO_PAD_MODE); - write32((void *)PCH_PCR_ADDRESS(PID_GPIOCOM1, + write32p(PCH_PCR_ADDRESS(PID_GPIOCOM1, R_PAD_CFG_DW0_UART0_RXD), reg32); } @@ -77,31 +77,31 @@ reg32 &= ~B_PCH_GPIO_PAD_MODE; reg32 |= (UINT32)(V_PCH_GPIO_PAD_MODE_NAT_1 << N_PCH_GPIO_PAD_MODE); - write32((void *)PCH_PCR_ADDRESS(PID_GPIOCOM1, + write32p(PCH_PCR_ADDRESS(PID_GPIOCOM1, R_PAD_CFG_DW0_UART0_TXD), reg32); } // UART0_CTS - reg32 = read32((void *)PCH_PCR_ADDRESS(PID_GPIOCOM1, + reg32 = read32p(PCH_PCR_ADDRESS(PID_GPIOCOM1, R_PAD_CFG_DW0_SMB3_CLTT_CLK)); if (((reg32 & B_PCH_GPIO_PAD_MODE) >> N_PCH_GPIO_PAD_MODE) != V_PCH_GPIO_PAD_MODE_NAT_2) { reg32 &= ~B_PCH_GPIO_PAD_MODE; reg32 |= (UINT32)(V_PCH_GPIO_PAD_MODE_NAT_2 << N_PCH_GPIO_PAD_MODE); - write32((void *)PCH_PCR_ADDRESS(PID_GPIOCOM1, + write32p(PCH_PCR_ADDRESS(PID_GPIOCOM1, R_PAD_CFG_DW0_SMB3_CLTT_CLK), reg32); } // UART0_RTS - reg32 = read32((void *)PCH_PCR_ADDRESS(PID_GPIOCOM1, + reg32 = read32p(PCH_PCR_ADDRESS(PID_GPIOCOM1, R_PAD_CFG_DW0_PCIE_CLKREQ5_N)); if (((reg32 & B_PCH_GPIO_PAD_MODE) >> N_PCH_GPIO_PAD_MODE) != V_PCH_GPIO_PAD_MODE_NAT_3) { reg32 &= ~B_PCH_GPIO_PAD_MODE; reg32 |= (UINT32)(V_PCH_GPIO_PAD_MODE_NAT_3 << N_PCH_GPIO_PAD_MODE); - write32((void *)PCH_PCR_ADDRESS(PID_GPIOCOM1, + write32p(PCH_PCR_ADDRESS(PID_GPIOCOM1, R_PAD_CFG_DW0_PCIE_CLKREQ5_N), reg32); } @@ -115,7 +115,7 @@ reg32 &= ~B_PCH_GPIO_PAD_MODE; reg32 |= (UINT32)(V_PCH_GPIO_PAD_MODE_NAT_1 << N_PCH_GPIO_PAD_MODE); - write32((void *)PCH_PCR_ADDRESS(PID_GPIOCOM1, + write32p(PCH_PCR_ADDRESS(PID_GPIOCOM1, R_PAD_CFG_DW0_UART1_RXD), reg32); } @@ -127,31 +127,31 @@ reg32 &= ~B_PCH_GPIO_PAD_MODE; reg32 |= (UINT32)(V_PCH_GPIO_PAD_MODE_NAT_1 << N_PCH_GPIO_PAD_MODE); - write32((void *)PCH_PCR_ADDRESS(PID_GPIOCOM1, + write32p(PCH_PCR_ADDRESS(PID_GPIOCOM1, R_PAD_CFG_DW0_UART1_TXD), reg32); } // UART1_CTS - reg32 = read32((void *)PCH_PCR_ADDRESS(PID_GPIOCOM1, + reg32 = read32p(PCH_PCR_ADDRESS(PID_GPIOCOM1, R_PAD_CFG_DW0_SATA1_SDOUT)); if (((reg32 & B_PCH_GPIO_PAD_MODE) >> N_PCH_GPIO_PAD_MODE) != V_PCH_GPIO_PAD_MODE_NAT_1) { reg32 &= ~B_PCH_GPIO_PAD_MODE; reg32 |= (UINT32)(V_PCH_GPIO_PAD_MODE_NAT_1 << N_PCH_GPIO_PAD_MODE); - write32((void *)PCH_PCR_ADDRESS(PID_GPIOCOM1, + write32p(PCH_PCR_ADDRESS(PID_GPIOCOM1, R_PAD_CFG_DW0_SATA1_SDOUT), reg32); } // UART1_RTS - reg32 = read32((void *)PCH_PCR_ADDRESS(PID_GPIOCOM1, + reg32 = read32p(PCH_PCR_ADDRESS(PID_GPIOCOM1, R_PAD_CFG_DW0_SATA0_SDOUT)); if (((reg32 & B_PCH_GPIO_PAD_MODE) >> N_PCH_GPIO_PAD_MODE) != V_PCH_GPIO_PAD_MODE_NAT_1) { reg32 &= ~B_PCH_GPIO_PAD_MODE; reg32 |= (UINT32)(V_PCH_GPIO_PAD_MODE_NAT_1 << N_PCH_GPIO_PAD_MODE); - write32((void *)PCH_PCR_ADDRESS(PID_GPIOCOM1, + write32p(PCH_PCR_ADDRESS(PID_GPIOCOM1, R_PAD_CFG_DW0_SATA0_SDOUT), reg32); } diff --git a/src/soc/intel/denverton_ns/gpio_dnv.c b/src/soc/intel/denverton_ns/gpio_dnv.c index 299f950..380e619 100644 --- a/src/soc/intel/denverton_ns/gpio_dnv.c +++ b/src/soc/intel/denverton_ns/gpio_dnv.c @@ -111,7 +111,7 @@ PadNumber %= 8; Mask = ((1 << 1) | (1 << 0)) << (PadNumber * 4);
- PadOwnRegValue = read32((void *)PCH_PCR_ADDRESS( + PadOwnRegValue = read32p(PCH_PCR_ADDRESS( GpioGroupInfo[GroupIndex].Community, RegOffset));
*PadOwnVal = (GPIO_PAD_OWN)((PadOwnRegValue & Mask) >> (PadNumber * 4)); @@ -379,7 +379,7 @@ // PadCfgReg = 0x8 * PadNumber + GpioGroupInfo[GroupIndex].PadCfgOffset; - Data32 = read32((void *)PCH_PCR_ADDRESS( + Data32 = read32p(PCH_PCR_ADDRESS( GpioGroupInfo[GroupIndex].Community, PadCfgReg));
FinalValue = ((Data32 & (~Dw0RegMask)) | Dw0Reg); @@ -408,7 +408,7 @@ ~(uint32_t)Dw0RegMask, (uint32_t)Dw0Reg); }
- Data32 = read32((void *)PCH_PCR_ADDRESS( + Data32 = read32p(PCH_PCR_ADDRESS( GpioGroupInfo[GroupIndex].Community, PadCfgReg + 0x4)); FinalValue = ((Data32 & (~Dw1RegMask)) | Dw1Reg); if (Data32 != FinalValue) { diff --git a/src/soc/intel/denverton_ns/lpc.c b/src/soc/intel/denverton_ns/lpc.c index 7ebca1e..7eeb3c2 100644 --- a/src/soc/intel/denverton_ns/lpc.c +++ b/src/soc/intel/denverton_ns/lpc.c @@ -320,60 +320,60 @@ config_t *config = config_of(dev);
/* Initialize PIRQ Routings */ - write8((void *)PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIRQA_ROUT), + write8p(PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIRQA_ROUT), config->pirqa_routing); - write8((void *)PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIRQB_ROUT), + write8p(PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIRQB_ROUT), config->pirqb_routing); - write8((void *)PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIRQC_ROUT), + write8p(PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIRQC_ROUT), config->pirqc_routing); - write8((void *)PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIRQD_ROUT), + write8p(PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIRQD_ROUT), config->pirqd_routing);
- write8((void *)PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIRQE_ROUT), + write8p(PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIRQE_ROUT), config->pirqe_routing); - write8((void *)PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIRQF_ROUT), + write8p(PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIRQF_ROUT), config->pirqf_routing); - write8((void *)PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIRQG_ROUT), + write8p(PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIRQG_ROUT), config->pirqg_routing); - write8((void *)PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIRQH_ROUT), + write8p(PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIRQH_ROUT), config->pirqh_routing);
/* Initialize device's Interrupt Routings */ - write16((void *)PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIR00), + write16p(PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIR00), config->ir00_routing); - write16((void *)PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIR01), + write16p(PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIR01), config->ir01_routing); - write16((void *)PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIR02), + write16p(PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIR02), config->ir02_routing); - write16((void *)PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIR03), + write16p(PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIR03), config->ir03_routing); - write16((void *)PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIR04), + write16p(PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIR04), config->ir04_routing); - write16((void *)PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIR05), + write16p(PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIR05), config->ir05_routing); - write16((void *)PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIR06), + write16p(PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIR06), config->ir06_routing); - write16((void *)PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIR07), + write16p(PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIR07), config->ir07_routing); - write16((void *)PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIR08), + write16p(PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIR08), config->ir08_routing); - write16((void *)PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIR09), + write16p(PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIR09), config->ir09_routing); - write16((void *)PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIR10), + write16p(PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIR10), config->ir10_routing); - write16((void *)PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIR11), + write16p(PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIR11), config->ir11_routing); - write16((void *)PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIR12), + write16p(PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIR12), config->ir12_routing);
/* Initialize device's Interrupt Polarity Control */ - write32((void *)PCH_PCR_ADDRESS(PID_ITSS, PCH_PCR_ITSS_IPC0), + write32p(PCH_PCR_ADDRESS(PID_ITSS, PCH_PCR_ITSS_IPC0), config->ipc0); - write32((void *)PCH_PCR_ADDRESS(PID_ITSS, PCH_PCR_ITSS_IPC1), + write32p(PCH_PCR_ADDRESS(PID_ITSS, PCH_PCR_ITSS_IPC1), config->ipc1); - write32((void *)PCH_PCR_ADDRESS(PID_ITSS, PCH_PCR_ITSS_IPC2), + write32p(PCH_PCR_ADDRESS(PID_ITSS, PCH_PCR_ITSS_IPC2), config->ipc2); - write32((void *)PCH_PCR_ADDRESS(PID_ITSS, PCH_PCR_ITSS_IPC3), + write32p(PCH_PCR_ADDRESS(PID_ITSS, PCH_PCR_ITSS_IPC3), config->ipc3);
for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) { diff --git a/src/soc/intel/denverton_ns/romstage.c b/src/soc/intel/denverton_ns/romstage.c index 2f3a5cc..20430b8 100644 --- a/src/soc/intel/denverton_ns/romstage.c +++ b/src/soc/intel/denverton_ns/romstage.c @@ -68,7 +68,7 @@ if (silicon_stepping() == SILICON_REV_DENVERTON_B0) { if (!(pci_read_config32(dev, GEN_PMCON_B) & GEN_PMCON_B_RTC_PWR_STS)) { - if (read32((void *)(pwrm_base + 0x124)) + if (read32p((pwrm_base + 0x124)) & ((1 << 11) | (1 << 12))) { /* Performs a global reset */ printk(BIOS_DEBUG, diff --git a/src/soc/intel/denverton_ns/sata.c b/src/soc/intel/denverton_ns/sata.c index 3fb5d75..ee4ef8f 100644 --- a/src/soc/intel/denverton_ns/sata.c +++ b/src/soc/intel/denverton_ns/sata.c @@ -39,9 +39,9 @@ printk(BIOS_DEBUG, "ABAR: %08X\n", abar);
/* Enable AHCI Mode */ - reg32 = read32((void *)(abar + 0x04)); + reg32 = read32p((abar + 0x04)); reg32 |= (1 << 31); - write32((void *)(abar + 0x04), reg32); + write32p((abar + 0x04), reg32); }
static void sata_enable(struct device *dev) { /* TODO */ } diff --git a/src/soc/intel/meteorlake/crashlog.c b/src/soc/intel/meteorlake/crashlog.c index 52d2371..b3159f5 100644 --- a/src/soc/intel/meteorlake/crashlog.c +++ b/src/soc/intel/meteorlake/crashlog.c @@ -5,6 +5,7 @@ #include <cpu/cpu.h> #include <cpu/intel/cpu_ids.h> #include <delay.h> +#include <device/mmio.h> #include <device/pci_ops.h> #include <intelblocks/crashlog.h> #include <intelblocks/pmc_ipc.h> @@ -34,7 +35,7 @@
static u64 get_disc_tab_header(void) { - return read64((void *)disc_tab_addr); + return read64p(disc_tab_addr); }
/* Get the SRAM BAR. */ @@ -362,7 +363,7 @@ break; }
- cpu_cl_disc_tab.buffers[i].data = read64((void *)(disc_tab_addr + cur_offset)); + cpu_cl_disc_tab.buffers[i].data = read64p((disc_tab_addr + cur_offset)); printk(BIOS_DEBUG, "cpu_crashlog_discovery_table buffer: 0x%x size: " "0x%x offset: 0x%x\n", i, cpu_cl_disc_tab.buffers[i].fields.size, cpu_cl_disc_tab.buffers[i].fields.offset); diff --git a/src/soc/intel/xeon_sp/spr/soc_acpi.c b/src/soc/intel/xeon_sp/spr/soc_acpi.c index 9d2df2c..0e10ab5 100644 --- a/src/soc/intel/xeon_sp/spr/soc_acpi.c +++ b/src/soc/intel/xeon_sp/spr/soc_acpi.c @@ -32,7 +32,7 @@ { /* PMC controller is hidden - hence PWRMBASE can't be accessbile using PCI cfg space */ uintptr_t pmc_bar = PCH_PWRM_BASE_ADDRESS; - return read32((void *)pmc_bar + PMC_ACPI_CNT); + return read32p(pmc_bar + PMC_ACPI_CNT); }
void soc_fill_fadt(acpi_fadt_t *fadt)