[M] Change in coreboot[master]: soc/intel/meteorlake: Log CSE RO write protection info for MTL - coreboot-gerrit

17 Nov 2022


      Attention is currently required from: Tarun Tuli, Subrata Banik, Sridhar Siricilla.
Kapil Porwal has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69571 )
Change subject: soc/intel/meteorlake: Log CSE RO write protection info for MTL
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Patch Set 6:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/69571/comment/559bbc94_6a3c6ceb 
PS2, Line 21: YES
...
It is the output of an existing API (is_spi_wp_cse_ro_en).
The output is indeed from google/rex board. The CL is ported from ADL.
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Idb072a873a8b8323532799f5fc64f995c9f0a604
Gerrit-Change-Number: 69571
Gerrit-PatchSet: 6
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