Change in coreboot[master]: mb/google/brya: Add UsbTcPortEn in devicetree

[EricR Lai (Code Review)]

EricR Lai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56074 )

Change subject: mb/google/brya: Add UsbTcPortEn in devicetree
......................................................................

mb/google/brya: Add UsbTcPortEn in devicetree

CB:2976591 add new parameter in FSP. Brya uses TCSS port 0/1/2,
we need to enable it in devicetree.

BUG=b:188481987
TEST=check typeC 3.0 works.

Signed-off-by: Eric Lai 
Change-Id: Ibe9d3a6d1d73cb37daae4a1ae49ee26abc43635b
---
M src/mainboard/google/brya/variants/baseboard/devicetree.cb
M src/soc/intel/alderlake/chip.h
M src/soc/intel/alderlake/fsp_params.c
3 files changed, 10 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/56074/1

diff --git a/src/mainboard/google/brya/variants/baseboard/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/devicetree.cb
index ce69213..2486b20 100644
--- a/src/mainboard/google/brya/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/brya/variants/baseboard/devicetree.cb
@@ -58,6 +58,9 @@
    register "tcss_ports[1]" = "TCSS_PORT_DEFAULT(OC1)"
    register "tcss_ports[2]" = "TCSS_PORT_DEFAULT(OC2)"

+	# TCSS USB3
+	register "UsbTcPortEn" = "0x7"
+
    register "SerialIoI2cMode" = "{
    	[PchSerialIoIndexI2C0] = PchSerialIoPci,
    	[PchSerialIoIndexI2C1] = PchSerialIoPci,
diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h
index 58daa25..ce9372a 100644
--- a/src/soc/intel/alderlake/chip.h
+++ b/src/soc/intel/alderlake/chip.h
@@ -112,6 +112,12 @@
    uint16_t usb3_wake_enable_bitmap;
    /* Program OC pins for TCSS */
    struct tcss_port_config tcss_ports[MAX_TYPE_C_PORTS];
+	/*
+	 * Specifies which Type-C Ports are enabled on the system
+	 * each bit represents a port starting at 0
+	 * Example: set value to 0x3 for ports 0 and 1 to be enabled
+	 */
+	uint8_t UsbTcPortEn;

/* SATA related */
    uint8_t SataEnable;
diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c
index e29133e..07aab22 100644
--- a/src/soc/intel/alderlake/fsp_params.c
+++ b/src/soc/intel/alderlake/fsp_params.c
@@ -289,6 +289,7 @@
 static void fill_fsps_tcss_params(FSP_S_CONFIG *s_cfg,
    	const struct soc_intel_alderlake_config *config)
 {
+	s_cfg->UsbTcPortEn = config->UsbTcPortEn;
    s_cfg->TcssAuxOri = config->TcssAuxOri;

/* Explicitly clear this field to avoid using defaults */