Change in coreboot[master]: soc/intel/{cnl,icl,skl,tgl}/bootblock: Update text for DMI PCR 2774 u...
Wim Vervoorn has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38747 )
Change subject: soc/intel/{cnl,icl,skl,tgl}/bootblock: Update text for DMI PCR 2774 update ......................................................................
soc/intel/{cnl,icl,skl,tgl}/bootblock: Update text for DMI PCR 2774 update
Make sure the Skylake comment refers to the correct BWG paragraph and update the text for all.
BUG=N/A TEST=build
Change-Id: Id383f200e079bdb91cea2240bd7a957d723a7b89 Signed-off-by: Wim Vervoorn wvervoorn@eltan.com --- M src/soc/intel/cannonlake/bootblock/pch.c M src/soc/intel/icelake/bootblock/pch.c M src/soc/intel/skylake/bootblock/pch.c M src/soc/intel/tigerlake/bootblock/pch.c 4 files changed, 9 insertions(+), 9 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/38747/1
diff --git a/src/soc/intel/cannonlake/bootblock/pch.c b/src/soc/intel/cannonlake/bootblock/pch.c index e7b79a0..eca28b3 100644 --- a/src/soc/intel/cannonlake/bootblock/pch.c +++ b/src/soc/intel/cannonlake/bootblock/pch.c @@ -168,8 +168,8 @@ if (pch_check_decode_enable() == 0) { io_enables = lpc_enable_fixed_io_ranges(io_enables); /* - * Set up LPC IO Enables PCR[DMI] + 2774h [15:0] to the same - * value program in LPC PCI offset 82h. + * Set LPC IO Enables PCR[DMI] + 2774h [15:0] to the same + * value programmed in LPC PCI offset 82h. */ pcr_write16(PID_DMI, PCR_DMI_LPCIOE, io_enables); /* diff --git a/src/soc/intel/icelake/bootblock/pch.c b/src/soc/intel/icelake/bootblock/pch.c index b1309a4..f51ecab 100644 --- a/src/soc/intel/icelake/bootblock/pch.c +++ b/src/soc/intel/icelake/bootblock/pch.c @@ -140,8 +140,8 @@ if (pch_check_decode_enable() == 0) { io_enables = lpc_enable_fixed_io_ranges(io_enables); /* - * Set up ESPI IO Enables PCR[DMI] + 2774h [15:0] to the same - * value program in ESPI PCI offset 82h. + * Set ESPI IO Enables PCR[DMI] + 2774h [15:0] to the same + * value programmed in ESPI PCI offset 82h. */ pcr_write16(PID_DMI, PCR_DMI_LPCIOE, io_enables); /* diff --git a/src/soc/intel/skylake/bootblock/pch.c b/src/soc/intel/skylake/bootblock/pch.c index 7763cf0..d5d3aed 100644 --- a/src/soc/intel/skylake/bootblock/pch.c +++ b/src/soc/intel/skylake/bootblock/pch.c @@ -135,9 +135,9 @@ if (pch_check_decode_enable() == 0) { io_enables = lpc_enable_fixed_io_ranges(io_enables); /* - * As per PCH BWG 2.5.16. - * Set up LPC IO Enables PCR[DMI] + 2774h [15:0] to the same - * value program in LPC PCI offset 82h. + * As per PCH BWG 2.5.1.6. + * Set LPC IO Enables PCR[DMI] + 2774h [15:0] to the same + * value programmed in LPC PCI offset 82h. */ pcr_write16(PID_DMI, PCR_DMI_LPCIOE, io_enables); /* diff --git a/src/soc/intel/tigerlake/bootblock/pch.c b/src/soc/intel/tigerlake/bootblock/pch.c index 8a132ce..ccdeadc 100644 --- a/src/soc/intel/tigerlake/bootblock/pch.c +++ b/src/soc/intel/tigerlake/bootblock/pch.c @@ -165,8 +165,8 @@ if (pch_check_decode_enable() == 0) { io_enables = lpc_enable_fixed_io_ranges(io_enables); /* - * Set up ESPI IO Enables PCR[DMI] + 2774h [15:0] to the same - * value program in ESPI PCI offset 82h. + * Set ESPI IO Enables PCR[DMI] + 2774h [15:0] to the same + * value programmed in ESPI PCI offset 82h. */ pcr_write16(PID_DMI, PCR_DMI_LPCIOE, io_enables); /*
Frans Hendriks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38747 )
Change subject: soc/intel/{cnl,icl,skl,tgl}/bootblock: Update text for DMI PCR 2774 update ......................................................................
Patch Set 1: Code-Review+2
Frans Hendriks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38747 )
Change subject: soc/intel/{cnl,icl,skl,tgl}/bootblock: Update text for DMI PCR 2774 update ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38747/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/38747/1//COMMIT_MSG@7 PS1, Line 7: soc/intel/{cnl,icl,skl,tgl}/bootblock: Update text for DMI PCR 2774 update remove second update
Hello Patrick Rudolph, Frans Hendriks, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38747
to look at the new patch set (#2).
Change subject: soc/intel/{cnl,icl,skl,tgl}/bootblock: Update text for DMI PCR 2774 ......................................................................
soc/intel/{cnl,icl,skl,tgl}/bootblock: Update text for DMI PCR 2774
Make sure the Skylake comment refers to the correct BWG paragraph and update the text for all.
BUG=N/A TEST=build
Change-Id: Id383f200e079bdb91cea2240bd7a957d723a7b89 Signed-off-by: Wim Vervoorn wvervoorn@eltan.com --- M src/soc/intel/cannonlake/bootblock/pch.c M src/soc/intel/icelake/bootblock/pch.c M src/soc/intel/skylake/bootblock/pch.c M src/soc/intel/tigerlake/bootblock/pch.c 4 files changed, 9 insertions(+), 9 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/38747/2
Wim Vervoorn has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38747 )
Change subject: soc/intel/{cnl,icl,skl,tgl}/bootblock: Update text for DMI PCR 2774 ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38747/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/38747/1//COMMIT_MSG@7 PS1, Line 7: soc/intel/{cnl,icl,skl,tgl}/bootblock: Update text for DMI PCR 2774 update
remove second update
Done
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/38747 )
Change subject: soc/intel/{cnl,icl,skl,tgl}/bootblock: Update text for DMI PCR 2774 ......................................................................
soc/intel/{cnl,icl,skl,tgl}/bootblock: Update text for DMI PCR 2774
Make sure the Skylake comment refers to the correct BWG paragraph and update the text for all.
BUG=N/A TEST=build
Change-Id: Id383f200e079bdb91cea2240bd7a957d723a7b89 Signed-off-by: Wim Vervoorn wvervoorn@eltan.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/38747 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Frans Hendriks fhendriks@eltan.com --- M src/soc/intel/cannonlake/bootblock/pch.c M src/soc/intel/icelake/bootblock/pch.c M src/soc/intel/skylake/bootblock/pch.c M src/soc/intel/tigerlake/bootblock/pch.c 4 files changed, 9 insertions(+), 9 deletions(-)
Approvals: build bot (Jenkins): Verified Frans Hendriks: Looks good to me, approved
diff --git a/src/soc/intel/cannonlake/bootblock/pch.c b/src/soc/intel/cannonlake/bootblock/pch.c index e7b79a0..eca28b3 100644 --- a/src/soc/intel/cannonlake/bootblock/pch.c +++ b/src/soc/intel/cannonlake/bootblock/pch.c @@ -168,8 +168,8 @@ if (pch_check_decode_enable() == 0) { io_enables = lpc_enable_fixed_io_ranges(io_enables); /* - * Set up LPC IO Enables PCR[DMI] + 2774h [15:0] to the same - * value program in LPC PCI offset 82h. + * Set LPC IO Enables PCR[DMI] + 2774h [15:0] to the same + * value programmed in LPC PCI offset 82h. */ pcr_write16(PID_DMI, PCR_DMI_LPCIOE, io_enables); /* diff --git a/src/soc/intel/icelake/bootblock/pch.c b/src/soc/intel/icelake/bootblock/pch.c index b1309a4..f51ecab 100644 --- a/src/soc/intel/icelake/bootblock/pch.c +++ b/src/soc/intel/icelake/bootblock/pch.c @@ -140,8 +140,8 @@ if (pch_check_decode_enable() == 0) { io_enables = lpc_enable_fixed_io_ranges(io_enables); /* - * Set up ESPI IO Enables PCR[DMI] + 2774h [15:0] to the same - * value program in ESPI PCI offset 82h. + * Set ESPI IO Enables PCR[DMI] + 2774h [15:0] to the same + * value programmed in ESPI PCI offset 82h. */ pcr_write16(PID_DMI, PCR_DMI_LPCIOE, io_enables); /* diff --git a/src/soc/intel/skylake/bootblock/pch.c b/src/soc/intel/skylake/bootblock/pch.c index 7763cf0..d5d3aed 100644 --- a/src/soc/intel/skylake/bootblock/pch.c +++ b/src/soc/intel/skylake/bootblock/pch.c @@ -135,9 +135,9 @@ if (pch_check_decode_enable() == 0) { io_enables = lpc_enable_fixed_io_ranges(io_enables); /* - * As per PCH BWG 2.5.16. - * Set up LPC IO Enables PCR[DMI] + 2774h [15:0] to the same - * value program in LPC PCI offset 82h. + * As per PCH BWG 2.5.1.6. + * Set LPC IO Enables PCR[DMI] + 2774h [15:0] to the same + * value programmed in LPC PCI offset 82h. */ pcr_write16(PID_DMI, PCR_DMI_LPCIOE, io_enables); /* diff --git a/src/soc/intel/tigerlake/bootblock/pch.c b/src/soc/intel/tigerlake/bootblock/pch.c index 33637e9..090f88f 100644 --- a/src/soc/intel/tigerlake/bootblock/pch.c +++ b/src/soc/intel/tigerlake/bootblock/pch.c @@ -165,8 +165,8 @@ if (pch_check_decode_enable() == 0) { io_enables = lpc_enable_fixed_io_ranges(io_enables); /* - * Set up ESPI IO Enables PCR[DMI] + 2774h [15:0] to the same - * value program in ESPI PCI offset 82h. + * Set ESPI IO Enables PCR[DMI] + 2774h [15:0] to the same + * value programmed in ESPI PCI offset 82h. */ pcr_write16(PID_DMI, PCR_DMI_LPCIOE, io_enables); /*
-
Frans Hendriks (Code Review) -
Patrick Georgi (Code Review)
-
Wim Vervoorn (Code Review)