Change in coreboot[master]: mb/pcengines/apu2/OemCustomize.c: make AGESA AmdInitPost happy

[Felix Held (Code Review)]

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52759 )

Change subject: mb/pcengines/apu2/OemCustomize.c: make AGESA AmdInitPost happy
......................................................................

mb/pcengines/apu2/OemCustomize.c: make AGESA AmdInitPost happy

Bank interleaving does not work on this platform, disable it.
Additionally enable ECC feature on SKUs supporting it. AmdIntPost
returns success thanks to these settings.

TEST=boot apu2 4GB ECC and apu3 2GB no ECC and see AGESA_SUCCESS after
AmdInitPost

Signed-off-by: Michał Żygowski 
Change-Id: I010645f53b404341895d0545855905e81c89165e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52759
Tested-by: build bot (Jenkins) 
Reviewed-by: Felix Held 
---
M src/mainboard/pcengines/apu2/OemCustomize.c
1 file changed, 16 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Felix Held: Looks good to me, approved

diff --git a/src/mainboard/pcengines/apu2/OemCustomize.c b/src/mainboard/pcengines/apu2/OemCustomize.c
index 6e6b5a2..95af6ef 100644
--- a/src/mainboard/pcengines/apu2/OemCustomize.c
+++ b/src/mainboard/pcengines/apu2/OemCustomize.c
@@ -3,6 +3,8 @@
 #include <AGESA.h>
 #include <northbridge/amd/agesa/state_machine.h>

+#include "gpio_ftns.h"
+
 static const PCIe_PORT_DESCRIPTOR PortList[] = {
    {
    	0,
@@ -78,3 +80,17 @@
    InitEarly->PlatformConfig.CStateMode = CStateModeC6;
    InitEarly->PlatformConfig.CpbMode = CpbModeAuto;
 }
+
+void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *Post)
+{
+	/*
+	 * Bank interleaving does not work on this platform.
+	 * Disable it so AGESA will return success.
+	 */
+	Post->MemConfig.EnableBankIntlv = FALSE;
+	/* 4GB variants have ECC */
+	if (get_spd_offset())
+		Post->MemConfig.EnableEccFeature = TRUE;
+	else
+		Post->MemConfig.EnableEccFeature = FALSE;
+}