[M] Change in coreboot[main]: soc/intel/pantherlake: Add core scaling factors read support

[Jérémy Compostella (Code Review)]

Jérémy Compostella has posted comments on this change by Jérémy Compostella. ( https://review.coreboot.org/c/coreboot/+/85554?usp=email )

Change subject: soc/intel/pantherlake: Add core scaling factors read support
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Patch Set 11:

(2 comments)

Patchset:

PS11:
> > Initially, I shared similar concerns when assigned this task. […]

This CL utilizes a BIOS mailbox command, a low-level interface not accessible by the Operating System. I believe it should be the responsibility of the IA firmware to provide an accurate hardware description, including performance and efficiency scaling factors. However, I acknowledge that the OS should not rely on BIOS for hardware initialization tasks that fall under the purview of OS device drivers.

File src/soc/intel/common/block/acpi/cpu_hybrid.c:

https://review.coreboot.org/c/coreboot/+/85554/comment/fc588146_83a86b43?usp... :
PS11, Line 18: enum cpu_perf_eff_type {
             : 	CPU_TYPE_EFF,
             : 	CPU_TYPE_PERF,
             : };
> It is, unfortunately, a bit late to take such a comment into account.

Closing as there is nothing we can do about it except reverting the whole thing and redoing the CLs but it seems overkill.