[S] Change in coreboot[main]: mb/google/fatcat/var/francka: Configure the finger print pins

[Ian Feng (Code Review)]

Ian Feng has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86413?usp=email )

Change subject: mb/google/fatcat/var/francka: Configure the finger print pins
......................................................................

mb/google/fatcat/var/francka: Configure the finger print pins

Configure correct finger print pins, And change power sequence.
FP_PWR_EN - GPP_H03
FP_RST_OD - GPP_H17
FPMCU_INT - GPP_D17
FPMCU_FW_UPDATE - GPP_F20

BUG=b:393985006
TEST=Boot to OS in francka and fingerprint function work well.

Change-Id: I0d9b1d042da1bd81d0f3a32140247948cdab983c
Signed-off-by: Ian Feng 
---
M src/mainboard/google/fatcat/variants/francka/gpio.c
M src/mainboard/google/fatcat/variants/francka/overridetree.cb
2 files changed, 20 insertions(+), 14 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/86413/1

diff --git a/src/mainboard/google/fatcat/variants/francka/gpio.c b/src/mainboard/google/fatcat/variants/francka/gpio.c
index 8819122..6265b16 100644
--- a/src/mainboard/google/fatcat/variants/francka/gpio.c
+++ b/src/mainboard/google/fatcat/variants/francka/gpio.c
@@ -186,7 +186,7 @@
    /* GPP_D16:     HDA_RST# */
    PAD_NC(GPP_D16, NONE),
    /* GPP_D17:     FPMCU_INT# */
-	PAD_CFG_GPI_INT(GPP_D17, NONE, PLTRST, LEVEL),
+	PAD_CFG_GPI_IRQ_WAKE(GPP_D17, NONE, PWROK, LEVEL, INVERT),
    /* GPP_D18:     CLKREQ_PCIE#6 */
    PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1),
    /* GPP_D19:     SOC_SD_RST# */
@@ -286,16 +286,16 @@
    PAD_NC(GPP_F14, NONE),
    /* GPP_F15:     Not used */
    PAD_NC(GPP_F15, NONE),
-	/* GPP_F16:     SOC_THC_1_RST# */
-	PAD_CFG_GPO(GPP_F16, 0, DEEP),
+	/* GPP_F16:     Not used */
+	PAD_NC(GPP_F16, NONE),
    /* GPP_F17:     SOC_THC_1_CS# */
    PAD_CFG_NF(GPP_F17, NONE, DEEP, NF5),
-	/* GPP_F18:     SOC_THC_1_INT# */
-	PAD_CFG_GPI_APIC(GPP_F18, NONE, PWROK, LEVEL, INVERT),
+	/* GPP_F18:     Not used */
+	PAD_NC(GPP_F18, NONE),
    /* GPP_F19:     Not used */
    PAD_NC(GPP_F19, NONE),
    /* GPP_F20:     AP_FP_FW_UP_STRAP */
-	PAD_CFG_GPO(GPP_F20, 1, DEEP),
+	PAD_CFG_GPO_LOCK(GPP_F20, 0, LOCK_CONFIG),
    /* GPP_F22:     Not used */
    PAD_NC(GPP_F22, NONE),
    /* GPP_F23:     SLP_S0#_GATE */
@@ -308,7 +308,7 @@
    /* GPP_H02:     Not used */
    PAD_NC(GPP_H02, NONE),
    /* GPP_H03:     EN_PWR_FP */
-	PAD_CFG_GPO(GPP_H03, 0, DEEP),
+	PAD_CFG_GPO(GPP_H03, 1, DEEP),
    /* GPP_H04:     COEX1 */
    PAD_CFG_NF(GPP_H04, NONE, DEEP, NF2),
    /* GPP_H05:     COEX2 */
@@ -334,7 +334,7 @@
    /* GPP_H16:     SOC_AUDIO_STRAP */
    PAD_CFG_GPI(GPP_H16, NONE, DEEP),
    /* GPP_H17:     FP_RST_1V8_OD# */
-	PAD_CFG_GPO(GPP_H17, 1, DEEP),
+	PAD_CFG_GPO_LOCK(GPP_H17, 1, LOCK_CONFIG),
    /* GPP_H19:     Not used*/
    PAD_NC(GPP_H19, NONE),
    /* GPP_H20:     Not used */
@@ -420,10 +420,10 @@
    PAD_CFG_NF(GPP_C00, NONE, DEEP, NF1),
    /* GPP_C01:     SOC_SMBDATA */
    PAD_CFG_NF(GPP_C01, NONE, DEEP, NF1),
-	/* GPP_F16:     SOC_THC_1_RST# */
-	PAD_CFG_GPO(GPP_F16, 0, DEEP),
    /* GPP_H03:     EN_PWR_FP */
    PAD_CFG_GPO(GPP_H03, 0, DEEP),
+	/* GPP_H17:     FP_RST_1V8_OD# */
+	PAD_CFG_GPO(GPP_H17, 0, DEEP),
 };

const struct pad_config *variant_gpio_table(size_t *num)
diff --git a/src/mainboard/google/fatcat/variants/francka/overridetree.cb b/src/mainboard/google/fatcat/variants/francka/overridetree.cb
index 58ced1a..580e96f 100644
--- a/src/mainboard/google/fatcat/variants/francka/overridetree.cb
+++ b/src/mainboard/google/fatcat/variants/francka/overridetree.cb
@@ -62,6 +62,12 @@
    	[PchSerialIoIndexI2C4]  = PchSerialIoPci,
    }"

+	register "serial_io_gspi_mode" = "{
+		[PchSerialIoIndexGSPI0] = PchSerialIoDisabled,
+		[PchSerialIoIndexGSPI1] = PchSerialIoPci,
+		[PchSerialIoIndexGSPI0A] = PchSerialIoDisabled,
+	}"
+
    # Intel Common SoC Config
    #+-------------------+---------------------------+
    #| Field             |  Value                    |
@@ -292,13 +298,13 @@
    			register "hid" = "ACPI_DT_NAMESPACE_HID"
    			register "uid" = "1"
    			register "compat_string" = ""google,cros-ec-spi""
-				register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F18_IRQ)"
-				register "wake" = "GPE0_DW2_15"
+				register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_D17_IRQ)"
+				register "wake" = "GPE0_DW1_17"
    			register "has_power_resource" = "true"
-				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F16)"
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H17)"
    			register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H03)"
    			register "enable_delay_ms" = "3"
-				device spi 0 hidden end
+				device spi 0 on end
    		end # FPMCU
    	end
    end