Bill XIE has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36992 )
Change subject: [WIP] mb/gigabyte/ga-b75m-d3h: Add ga-b75-d3v as a variant ......................................................................
[WIP] mb/gigabyte/ga-b75m-d3h: Add ga-b75-d3v as a variant
It is an ATX board similar to existing ga-b75* boards. The major difference is the configuration of pci-e ports on PCH, and on-board pci-e NIC. (see below)
Tested: - CPU i5 3570T - Slotted DIMM 8GiB*4 from Kingston - usb2 and usb3 - libgfxinit-based graphic init - NVRAM options for North and South bridges - tpm 1.2 on lpc (similar to ga-b75m-d3h) - Linux 4.19.67-2 within Debian GNU/Linux stable, loaded from Seabios.
Should work: - sata - Sound - S3
Unstable: - some pci-e devices connected to pch (including the AR8161 below attached to 1c.2) breaks RTC init and causes hang in mc146818rtc.c:__cmos_init(), possibly related to power consumption.
TODO: Add AR8161 support. (it is supported by driver "alx" in Linux kernel, and the logic to set mac address is essentially identical to the one for atl1e, but the logic to detect address burned in efuse and external rom are different)
Change-Id: I1a969880e4da02abf8ba73aac60ee1296fe0abf2 Signed-off-by: Bill XIE persmule@hardenedlinux.org --- M src/mainboard/gigabyte/ga-b75m-d3h/Kconfig M src/mainboard/gigabyte/ga-b75m-d3h/Kconfig.name A src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75-d3v/board_info.txt A src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75-d3v/gma-mainboard.ads A src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75-d3v/gpio.c A src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75-d3v/include/variant/hda_verb.h A src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75-d3v/overridetree.cb A src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75m-d3h/overridetree.cb A src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75m-d3v/overridetree.cb 9 files changed, 348 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/36992/1
diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/Kconfig b/src/mainboard/gigabyte/ga-b75m-d3h/Kconfig index ceb2dbc..7fd030a 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/Kconfig +++ b/src/mainboard/gigabyte/ga-b75m-d3h/Kconfig @@ -1,4 +1,4 @@ -if BOARD_GIGABYTE_GA_B75M_D3H || BOARD_GIGABYTE_GA_B75M_D3V +if BOARD_GIGABYTE_GA_B75M_D3H || BOARD_GIGABYTE_GA_B75M_D3V || BOARD_GIGABYTE_GA_B75_D3V
config BOARD_SPECIFIC_OPTIONS def_bool y @@ -34,11 +34,17 @@ string default "ga-b75m-d3h" if BOARD_GIGABYTE_GA_B75M_D3H default "ga-b75m-d3v" if BOARD_GIGABYTE_GA_B75M_D3V + default "ga-b75-d3v" if BOARD_GIGABYTE_GA_B75_D3V
config MAINBOARD_PART_NUMBER string default "GA-B75M-D3H" if BOARD_GIGABYTE_GA_B75M_D3H default "GA-B75M-D3V" if BOARD_GIGABYTE_GA_B75M_D3V + default "GA-B75-D3V" if BOARD_GIGABYTE_GA_B75_D3V + +config OVERRIDE_DEVICETREE + string + default "variants/$(CONFIG_VARIANT_DIR)/overridetree.cb"
config MAX_CPUS int @@ -49,4 +55,4 @@ string default "src/mainboard/$(MAINBOARDDIR)/data.vbt"
-endif # BOARD_GIGABYTE_GA_B75M* +endif # BOARD_GIGABYTE_GA_B75* diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/Kconfig.name b/src/mainboard/gigabyte/ga-b75m-d3h/Kconfig.name index f8fbe54..93f73a5 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/Kconfig.name +++ b/src/mainboard/gigabyte/ga-b75m-d3h/Kconfig.name @@ -3,3 +3,6 @@
config BOARD_GIGABYTE_GA_B75M_D3V bool "GA-B75M-D3V" + +config BOARD_GIGABYTE_GA_B75_D3V + bool "GA-B75-D3V" diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75-d3v/board_info.txt b/src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75-d3v/board_info.txt new file mode 100644 index 0000000..f90483f --- /dev/null +++ b/src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75-d3v/board_info.txt @@ -0,0 +1,7 @@ +Category: desktop +Board URL: https://www.gigabyte.com/Motherboard/GA-B75-D3V-rev-11 +ROM package: SOIC-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: y +Release year: 2012 diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75-d3v/gma-mainboard.ads b/src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75-d3v/gma-mainboard.ads new file mode 100644 index 0000000..416732d --- /dev/null +++ b/src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75-d3v/gma-mainboard.ads @@ -0,0 +1,28 @@ +-- +-- Copyright (C) 2017 Bill XIE persmule@gmail.com +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (HDMI1, + Analog, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75-d3v/gpio.c b/src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75-d3v/gpio.c new file mode 100644 index 0000000..763dfad --- /dev/null +++ b/src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75-d3v/gpio.c @@ -0,0 +1,201 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_NATIVE, + .gpio3 = GPIO_MODE_NATIVE, + .gpio4 = GPIO_MODE_NATIVE, + .gpio5 = GPIO_MODE_NATIVE, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_NATIVE, + .gpio11 = GPIO_MODE_NATIVE, + .gpio12 = GPIO_MODE_GPIO, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_NATIVE, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_GPIO, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_NATIVE, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_OUTPUT, + .gpio12 = GPIO_DIR_OUTPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_OUTPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio19 = GPIO_DIR_INPUT, + .gpio21 = GPIO_DIR_INPUT, + .gpio22 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio29 = GPIO_DIR_INPUT, + .gpio31 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio8 = GPIO_LEVEL_HIGH, + .gpio12 = GPIO_LEVEL_HIGH, + .gpio15 = GPIO_LEVEL_LOW, + .gpio24 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { + .gpio24 = GPIO_RESET_RSMRST, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio13 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_GPIO, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_GPIO, + .gpio37 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_NATIVE, + .gpio45 = GPIO_MODE_NATIVE, + .gpio46 = GPIO_MODE_NATIVE, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_NATIVE, + .gpio51 = GPIO_MODE_NATIVE, + .gpio52 = GPIO_MODE_NATIVE, + .gpio53 = GPIO_MODE_NATIVE, + .gpio54 = GPIO_MODE_NATIVE, + .gpio55 = GPIO_MODE_NATIVE, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_NATIVE, + .gpio61 = GPIO_MODE_NATIVE, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_OUTPUT, + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio35 = GPIO_DIR_OUTPUT, + .gpio36 = GPIO_DIR_INPUT, + .gpio37 = GPIO_DIR_INPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio48 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio32 = GPIO_LEVEL_HIGH, + .gpio33 = GPIO_LEVEL_HIGH, + .gpio35 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_NATIVE, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_NATIVE, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_NATIVE, + .gpio71 = GPIO_MODE_NATIVE, + .gpio72 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_NATIVE, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio72 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75-d3v/include/variant/hda_verb.h b/src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75-d3v/include/variant/hda_verb.h new file mode 100644 index 0000000..c92c625 --- /dev/null +++ b/src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75-d3v/include/variant/hda_verb.h @@ -0,0 +1,69 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef GA_B75_D3V_HDA_VERB_H +#define GA_B75_D3V_HDA_VERB_H + +const u32 cim_verb_data[] = { + /* coreboot specific header */ + 0x10ec0887, // Realtek 887 + 0x1458a002, // Subsystem ID + 0x0000000e, // Number of entries + + /* NID 0x01: Subsystem ID. */ + AZALIA_SUBVENDOR(0x2, 0x1458a002), + + /* NID 0x11. */ + AZALIA_PIN_CFG(0x2, 0x11, 0x99430130), + + /* NID 0x12. */ + AZALIA_PIN_CFG(0x2, 0x12, 0x411111f0), + + /* NID 0x14. */ + AZALIA_PIN_CFG(0x2, 0x14, 0x01014410), + + /* NID 0x15. */ + AZALIA_PIN_CFG(0x2, 0x15, 0x411111f0), + + /* NID 0x16. */ + AZALIA_PIN_CFG(0x2, 0x16, 0x411111f0), + + /* NID 0x17. */ + AZALIA_PIN_CFG(0x2, 0x17, 0x411111f0), + + /* NID 0x18. */ + AZALIA_PIN_CFG(0x2, 0x18, 0x01a19c50), + + /* NID 0x19. */ + AZALIA_PIN_CFG(0x2, 0x19, 0x02a19c60), + + /* NID 0x1a. */ + AZALIA_PIN_CFG(0x2, 0x1a, 0x0181345f), + + /* NID 0x1b. */ + AZALIA_PIN_CFG(0x2, 0x1b, 0x02214c20), + + /* NID 0x1c. */ + AZALIA_PIN_CFG(0x2, 0x1c, 0x411111f0), + + /* NID 0x1d. */ + AZALIA_PIN_CFG(0x2, 0x1d, 0x4004c601), + + /* NID 0x1e. */ + AZALIA_PIN_CFG(0x2, 0x1e, 0x411111f0), + + /* NID 0x1f. */ + AZALIA_PIN_CFG(0x2, 0x1f, 0x411111f0), +}; + +#endif diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75-d3v/overridetree.cb b/src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75-d3v/overridetree.cb new file mode 100644 index 0000000..e5b7285 --- /dev/null +++ b/src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75-d3v/overridetree.cb @@ -0,0 +1,26 @@ +chip northbridge/intel/sandybridge + device domain 0 on + chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH + device pci 16.0 off end # Management Engine Interface 1 + register "xhci_overcurrent_mapping" = "0x00000c03" + device pci 1c.1 on end # PCIe Port #2 + device pci 1c.2 on + device pci 00.0 on # PCI 1969:1091 + subsystemid 0x1458 0xe000 + end + end # PCIe Port #3 + device pci 1c.3 on end # PCIe Port #4 + device pci 1c.4 on end # PCIe Port #5 + device pci 1f.0 on # ISA/LPC bridge + subsystemid 0x1458 0x5001 + chip superio/ite/it8728f + device pnp 2e.2 off end # COM2 + device pnp 2e.3 off end # LPT + device pnp 2e.4 on # EC + io 0x62 = 0x230 + end + end + end + end + end +end diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75m-d3h/overridetree.cb b/src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75m-d3h/overridetree.cb new file mode 100644 index 0000000..dbe35ba --- /dev/null +++ b/src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75m-d3h/overridetree.cb @@ -0,0 +1,3 @@ +chip northbridge/intel/sandybridge + device domain 0 on end +end \ No newline at end of file diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75m-d3v/overridetree.cb b/src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75m-d3v/overridetree.cb new file mode 100644 index 0000000..dbe35ba --- /dev/null +++ b/src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75m-d3v/overridetree.cb @@ -0,0 +1,3 @@ +chip northbridge/intel/sandybridge + device domain 0 on end +end \ No newline at end of file
Bill XIE has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36992 )
Change subject: [WIP] mb/gigabyte/ga-b75m-d3h: Add ga-b75-d3v as a variant ......................................................................
Patch Set 2:
To trigger a build testing.
Bill XIE has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/36992 )
Change subject: [WIP] mb/gigabyte/ga-b75m-d3h: Add ga-b75-d3v as a variant ......................................................................
Abandoned
require another commit
Bill XIE has restored this change. ( https://review.coreboot.org/c/coreboot/+/36992 )
Change subject: [WIP] mb/gigabyte/ga-b75m-d3h: Add ga-b75-d3v as a variant ......................................................................
Restored
Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/36992
to look at the new patch set (#3).
Change subject: mb/gigabyte/ga-b75m-d3h: Add ga-b75-d3v as a variant ......................................................................
mb/gigabyte/ga-b75m-d3h: Add ga-b75-d3v as a variant
It is an ATX board similar to existing ga-b75* boards. The major difference is the configuration of pci-e ports on PCH, and on-board pci-e NIC. (see below)
Tested: - CPU i5 3570T - Slotted DIMM 8GiB*4 from Kingston - usb2 and usb3 - pci and pci-e ports - Sound - AR8161 NIC connected to 1c.2 with mac address burnt in efuse - libgfxinit-based graphic init - NVRAM options for North and South bridges - tpm 1.2 on lpc (similar to ga-b75m-d3h) - Linux 4.19.67-2 within Debian GNU/Linux stable, loaded from Seabios.
Should work: - sata - S3
Change-Id: I1a969880e4da02abf8ba73aac60ee1296fe0abf2 Signed-off-by: Bill XIE persmule@hardenedlinux.org --- M src/mainboard/gigabyte/ga-b75m-d3h/Kconfig M src/mainboard/gigabyte/ga-b75m-d3h/Kconfig.name A src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75-d3v/board_info.txt A src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75-d3v/gma-mainboard.ads A src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75-d3v/gpio.c A src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75-d3v/include/variant/hda_verb.h A src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75-d3v/overridetree.cb A src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75m-d3h/overridetree.cb A src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75m-d3v/overridetree.cb 9 files changed, 348 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/36992/3
Bill XIE has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36992 )
Change subject: mb/gigabyte/ga-b75m-d3h: Add ga-b75-d3v as a variant ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/36992/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/36992/2//COMMIT_MSG@29 PS2, Line 29: - some pci-e devices connected to pch (including the AR8161 It turns out caused by an ill device tree compiled by a buggy sconfig, which is fixed in CB:37109.
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36992 )
Change subject: mb/gigabyte/ga-b75m-d3h: Add ga-b75-d3v as a variant ......................................................................
Patch Set 3: Code-Review+1
(1 comment)
https://review.coreboot.org/c/coreboot/+/36992/3//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/36992/3//COMMIT_MSG@24 PS3, Line 24: Seabios SeaBIOS
Hello Paul Menzel, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/36992
to look at the new patch set (#5).
Change subject: mb/gigabyte/ga-b75m-d3h: Add ga-b75-d3v as a variant ......................................................................
mb/gigabyte/ga-b75m-d3h: Add ga-b75-d3v as a variant
It is an ATX board similar to existing ga-b75* boards. The major difference is the configuration of pci-e ports on PCH, and on-board pci-e NIC. (see below)
Tested: - CPU i5 3570T - Slotted DIMM 8GiB*4 from Kingston - usb2 and usb3 - pci and pci-e ports - Sound - AR8161 NIC connected to 1c.2 with mac address burnt in efuse - libgfxinit-based graphic init - NVRAM options for North and South bridges - tpm 1.2 on lpc (similar to ga-b75m-d3h) - Linux 4.19.67-2 within Debian GNU/Linux stable, loaded from SeaBIOS.
Should work: - sata - S3
Change-Id: I1a969880e4da02abf8ba73aac60ee1296fe0abf2 Signed-off-by: Bill XIE persmule@hardenedlinux.org --- M src/mainboard/gigabyte/ga-b75m-d3h/Kconfig M src/mainboard/gigabyte/ga-b75m-d3h/Kconfig.name A src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75-d3v/board_info.txt A src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75-d3v/gma-mainboard.ads A src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75-d3v/gpio.c A src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75-d3v/include/variant/hda_verb.h A src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75-d3v/overridetree.cb A src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75m-d3h/overridetree.cb A src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75m-d3v/overridetree.cb 9 files changed, 348 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/36992/5
Bill XIE has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36992 )
Change subject: mb/gigabyte/ga-b75m-d3h: Add ga-b75-d3v as a variant ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/c/coreboot/+/36992/3//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/36992/3//COMMIT_MSG@24 PS3, Line 24: Seabios
SeaBIOS
Done
Bill XIE has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36992 )
Change subject: mb/gigabyte/ga-b75m-d3h: Add ga-b75-d3v as a variant ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/c/coreboot/+/36992/5/src/mainboard/gigabyte/ga-b... File src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75-d3v/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/36992/5/src/mainboard/gigabyte/ga-b... PS5, Line 20: io 0x62 = 0x230 This needs CB:37109 to build correctly, otherwise this "io 0x62 = 0x230" for device pnp 2e.4 in override tree will be mistakenly overrided to "io 0x60 = 0xa30" in base tree, creating two resources for io 0x62 and none for io 0x60.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36992 )
Change subject: mb/gigabyte/ga-b75m-d3h: Add ga-b75-d3v as a variant ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/c/coreboot/+/36992/5/src/mainboard/gigabyte/ga-b... File src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75-d3v/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/36992/5/src/mainboard/gigabyte/ga-b... PS5, Line 20: io 0x62 = 0x230
This needs CB:37109 to build correctly, otherwise this "io 0x62 = 0x230" for device pnp 2e. […]
How about explicitly setting both io resources here?
Bill XIE has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36992 )
Change subject: mb/gigabyte/ga-b75m-d3h: Add ga-b75-d3v as a variant ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/c/coreboot/+/36992/5/src/mainboard/gigabyte/ga-b... File src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75-d3v/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/36992/5/src/mainboard/gigabyte/ga-b... PS5, Line 20: io 0x62 = 0x230
How about explicitly setting both io resources here?
The latter resource will override the former with the same type. You can reproduce this behavior with the sconfig prior to CB:37109.
Bill XIE has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36992 )
Change subject: mb/gigabyte/ga-b75m-d3h: Add ga-b75-d3v as a variant ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/c/coreboot/+/36992/5/src/mainboard/gigabyte/ga-b... File src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75-d3v/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/36992/5/src/mainboard/gigabyte/ga-b... PS5, Line 20: io 0x62 = 0x230
The latter resource will override the former with the same type. […]
After CB:37109, setting resources here or in base tree makes no real difference.
Bill XIE has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36992 )
Change subject: mb/gigabyte/ga-b75m-d3h: Add ga-b75-d3v as a variant ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/c/coreboot/+/36992/5/src/mainboard/gigabyte/ga-b... File src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75-d3v/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/36992/5/src/mainboard/gigabyte/ga-b... PS5, Line 20: io 0x62 = 0x230
After CB:37109, setting resources here or in base tree makes no real difference.
Before CB:37109, setting more than one resources with the same type in override tree does not work, and only one will remain in the compilation result. You can reproduce this behavior by invoking $ make build/mainboard/${MAINBOARDDIR}/static.c and checking the generated static.c.
Hello Paul Menzel, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/36992
to look at the new patch set (#6).
Change subject: mb/gigabyte/ga-b75m-d3h: Add ga-b75-d3v as a variant ......................................................................
mb/gigabyte/ga-b75m-d3h: Add ga-b75-d3v as a variant
It is an ATX board similar to existing ga-b75* boards. The major difference is the configuration of pci-e ports on PCH, and on-board pci-e NIC. (see below)
Tested: - CPU i5 3570T - Slotted DIMM 8GiB*4 from Kingston - usb2 and usb3 - pci and pci-e ports - sata - Sound - AR8161 NIC connected to 1c.2 with mac address burnt in efuse - libgfxinit-based graphic init - NVRAM options for North and South bridges - tpm 1.2 on lpc (similar to ga-b75m-d3h) - Linux 4.19.67-2 within Debian GNU/Linux stable, loaded from SeaBIOS.
Should work: - S3
Change-Id: I1a969880e4da02abf8ba73aac60ee1296fe0abf2 Signed-off-by: Bill XIE persmule@hardenedlinux.org --- M src/mainboard/gigabyte/ga-b75m-d3h/Kconfig M src/mainboard/gigabyte/ga-b75m-d3h/Kconfig.name A src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75-d3v/board_info.txt A src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75-d3v/gma-mainboard.ads A src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75-d3v/gpio.c A src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75-d3v/include/variant/hda_verb.h A src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75-d3v/overridetree.cb A src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75m-d3h/overridetree.cb A src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75m-d3v/overridetree.cb 9 files changed, 348 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/36992/6
Hello Paul Menzel, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/36992
to look at the new patch set (#7).
Change subject: mb/gigabyte/ga-b75m-d3h: Add ga-b75-d3v as a variant ......................................................................
mb/gigabyte/ga-b75m-d3h: Add ga-b75-d3v as a variant
It is an ATX board similar to existing ga-b75* boards. The major difference is the configuration of pci-e ports on PCH, and on-board pci-e NIC. (see below)
Tested: - CPU i5 3570T - Slotted DIMM 8GiB*4 from Kingston - usb2 and usb3 - pci and pci-e ports - sata - Sound - S3 - AR8161 NIC connected to 1c.2 with mac address burnt in efuse - libgfxinit-based graphic init - NVRAM options for North and South bridges - tpm 1.2 on lpc (similar to ga-b75m-d3h) - Linux 4.19.67-2 within Debian GNU/Linux stable, loaded from SeaBIOS.
Change-Id: I1a969880e4da02abf8ba73aac60ee1296fe0abf2 Signed-off-by: Bill XIE persmule@hardenedlinux.org --- M src/mainboard/gigabyte/ga-b75m-d3h/Kconfig M src/mainboard/gigabyte/ga-b75m-d3h/Kconfig.name A src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75-d3v/board_info.txt A src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75-d3v/gma-mainboard.ads A src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75-d3v/gpio.c A src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75-d3v/include/variant/hda_verb.h A src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75-d3v/overridetree.cb A src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75m-d3h/overridetree.cb A src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75m-d3v/overridetree.cb 9 files changed, 348 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/36992/7
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36992 )
Change subject: mb/gigabyte/ga-b75m-d3h: Add ga-b75-d3v as a variant ......................................................................
Patch Set 9: Code-Review+1
(3 comments)
Looks good.
https://review.coreboot.org/c/coreboot/+/36992/9/src/mainboard/gigabyte/ga-b... File src/mainboard/gigabyte/ga-b75m-d3h/Kconfig:
https://review.coreboot.org/c/coreboot/+/36992/9/src/mainboard/gigabyte/ga-b... PS9, Line 47: default "variants/$(CONFIG_VARIANT_DIR)/overridetree.cb" you can make this conditional if you are not overriding things on some boards.
https://review.coreboot.org/c/coreboot/+/36992/9/src/mainboard/gigabyte/ga-b... File src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75-d3v/include/variant/hda_verb.h:
https://review.coreboot.org/c/coreboot/+/36992/9/src/mainboard/gigabyte/ga-b... PS9, Line 26: /* NID 0x11. */ IMO these are redundant.
https://review.coreboot.org/c/coreboot/+/36992/9/src/mainboard/gigabyte/ga-b... File src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75-d3v/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/36992/9/src/mainboard/gigabyte/ga-b... PS9, Line 20: io 0x62 = 0x230 is it really necessary to override this? There is nothing else set up to decode this.
Hello Arthur Heymans, Paul Menzel, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/36992
to look at the new patch set (#10).
Change subject: mb/gigabyte/ga-b75m-d3h: Add ga-b75-d3v as a variant ......................................................................
mb/gigabyte/ga-b75m-d3h: Add ga-b75-d3v as a variant
It is an ATX board similar to existing ga-b75* boards. The major difference is the configuration of pci-e ports on PCH, and on-board pci-e NIC. (see below)
Tested: - CPU i5 3570T - Slotted DIMM 8GiB*4 from Kingston - usb2 and usb3 - pci and pci-e ports - sata - Sound - S3 - AR8161 NIC connected to 1c.2 with mac address burnt in efuse - libgfxinit-based graphic init - NVRAM options for North and South bridges - tpm 1.2 on lpc (similar to ga-b75m-d3h) - Linux 4.19.67-2 within Debian GNU/Linux stable, loaded from SeaBIOS.
Change-Id: I1a969880e4da02abf8ba73aac60ee1296fe0abf2 Signed-off-by: Bill XIE persmule@hardenedlinux.org --- M src/mainboard/gigabyte/ga-b75m-d3h/Kconfig M src/mainboard/gigabyte/ga-b75m-d3h/Kconfig.name A src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75-d3v/board_info.txt A src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75-d3v/gma-mainboard.ads A src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75-d3v/gpio.c A src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75-d3v/include/variant/hda_verb.h A src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75-d3v/overridetree.cb 7 files changed, 342 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/36992/10
Bill XIE has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36992 )
Change subject: mb/gigabyte/ga-b75m-d3h: Add ga-b75-d3v as a variant ......................................................................
Patch Set 10:
(3 comments)
https://review.coreboot.org/c/coreboot/+/36992/9/src/mainboard/gigabyte/ga-b... File src/mainboard/gigabyte/ga-b75m-d3h/Kconfig:
https://review.coreboot.org/c/coreboot/+/36992/9/src/mainboard/gigabyte/ga-b... PS9, Line 47: default "variants/$(CONFIG_VARIANT_DIR)/overridetree.cb"
you can make this conditional if you are not overriding things on some boards.
Done
https://review.coreboot.org/c/coreboot/+/36992/9/src/mainboard/gigabyte/ga-b... File src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75-d3v/include/variant/hda_verb.h:
https://review.coreboot.org/c/coreboot/+/36992/9/src/mainboard/gigabyte/ga-b... PS9, Line 26: /* NID 0x11. */
IMO these are redundant.
Which are redundant?
https://review.coreboot.org/c/coreboot/+/36992/9/src/mainboard/gigabyte/ga-b... File src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75-d3v/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/36992/9/src/mainboard/gigabyte/ga-b... PS9, Line 20: io 0x62 = 0x230
is it really necessary to override this? There is nothing else set up to decode this.
The superiotool dump when running vendor firmware says so.
Hello Arthur Heymans, Paul Menzel, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/36992
to look at the new patch set (#11).
Change subject: mb/gigabyte/ga-b75m-d3h: Add ga-b75-d3v as a variant ......................................................................
mb/gigabyte/ga-b75m-d3h: Add ga-b75-d3v as a variant
It is an ATX board similar to existing ga-b75* boards. The major difference is the configuration of pci-e ports on PCH, and on-board pci-e NIC. (see below)
Tested: - CPU i5 3570T - Slotted DIMM 8GiB*4 from Kingston - usb2 and usb3 - pci and pci-e ports - sata - Sound - S3 - AR8161 NIC connected to 1c.2 with mac address burnt in efuse - libgfxinit-based graphic init - NVRAM options for North and South bridges - tpm 1.2 on lpc (similar to ga-b75m-d3h) - Linux 4.19.67-2 within Debian GNU/Linux stable, loaded from SeaBIOS.
Change-Id: I1a969880e4da02abf8ba73aac60ee1296fe0abf2 Signed-off-by: Bill XIE persmule@hardenedlinux.org --- M src/mainboard/gigabyte/ga-b75m-d3h/Kconfig M src/mainboard/gigabyte/ga-b75m-d3h/Kconfig.name A src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75-d3v/board_info.txt A src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75-d3v/gma-mainboard.ads A src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75-d3v/gpio.c A src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75-d3v/include/variant/hda_verb.h A src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75-d3v/overridetree.cb 7 files changed, 316 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/36992/11
Bill XIE has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36992 )
Change subject: mb/gigabyte/ga-b75m-d3h: Add ga-b75-d3v as a variant ......................................................................
Patch Set 11:
(1 comment)
https://review.coreboot.org/c/coreboot/+/36992/9/src/mainboard/gigabyte/ga-b... File src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75-d3v/include/variant/hda_verb.h:
https://review.coreboot.org/c/coreboot/+/36992/9/src/mainboard/gigabyte/ga-b... PS9, Line 26: /* NID 0x11. */
Which are redundant?
Redundant comments removed.
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36992 )
Change subject: mb/gigabyte/ga-b75m-d3h: Add ga-b75-d3v as a variant ......................................................................
Patch Set 11:
(1 comment)
https://review.coreboot.org/c/coreboot/+/36992/9/src/mainboard/gigabyte/ga-b... File src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75-d3v/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/36992/9/src/mainboard/gigabyte/ga-b... PS9, Line 20: io 0x62 = 0x230
The superiotool dump when running vendor firmware says so.
I would expect another genx_dec to cover that range then? It's supposed to be configurable so using the already working '0xa20' should be fine.
Hello Arthur Heymans, Paul Menzel, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/36992
to look at the new patch set (#12).
Change subject: mb/gigabyte/ga-b75m-d3h: Add ga-b75-d3v as a variant ......................................................................
mb/gigabyte/ga-b75m-d3h: Add ga-b75-d3v as a variant
It is an ATX board similar to existing ga-b75* boards. The major difference is the configuration of pci-e ports on PCH, and on-board pci-e NIC. (see below)
Tested: - CPU i5 3570T - Slotted DIMM 8GiB*4 from Kingston - usb2 and usb3 - pci and pci-e ports - sata - Sound - S3 - AR8161 NIC connected to 1c.2 with mac address burnt in efuse - libgfxinit-based graphic init - NVRAM options for North and South bridges - tpm 1.2 on lpc (similar to ga-b75m-d3h) - Linux 4.19.67-2 within Debian GNU/Linux stable, loaded from SeaBIOS.
Change-Id: I1a969880e4da02abf8ba73aac60ee1296fe0abf2 Signed-off-by: Bill XIE persmule@hardenedlinux.org --- M src/mainboard/gigabyte/ga-b75m-d3h/Kconfig M src/mainboard/gigabyte/ga-b75m-d3h/Kconfig.name A src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75-d3v/board_info.txt A src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75-d3v/gma-mainboard.ads A src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75-d3v/gpio.c A src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75-d3v/include/variant/hda_verb.h A src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75-d3v/overridetree.cb 7 files changed, 313 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/36992/12
Hello Arthur Heymans, Paul Menzel, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/36992
to look at the new patch set (#13).
Change subject: mb/gigabyte/ga-b75m-d3h: Add ga-b75-d3v as a variant ......................................................................
mb/gigabyte/ga-b75m-d3h: Add ga-b75-d3v as a variant
It is an ATX board similar to existing ga-b75* boards. The major difference is the configuration of pci-e ports on PCH, and on-board pci-e NIC. (see below)
Tested: - CPU i5 3570T - Slotted DIMM 8GiB*4 from Kingston - usb2 and usb3 - pci and pci-e ports - sata - Sound - S3 - AR8161 NIC connected to 1c.2 with mac address burnt in efuse - libgfxinit-based graphic init - NVRAM options for North and South bridges - tpm 1.2 on lpc (similar to ga-b75m-d3h) - Linux 4.19.67-2 within Debian GNU/Linux stable, loaded from SeaBIOS.
Change-Id: I1a969880e4da02abf8ba73aac60ee1296fe0abf2 Signed-off-by: Bill XIE persmule@hardenedlinux.org --- M src/mainboard/gigabyte/ga-b75m-d3h/Kconfig M src/mainboard/gigabyte/ga-b75m-d3h/Kconfig.name A src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75-d3v/board_info.txt A src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75-d3v/gma-mainboard.ads A src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75-d3v/gpio.c A src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75-d3v/include/variant/hda_verb.h A src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75-d3v/overridetree.cb 7 files changed, 313 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/36992/13
Bill XIE has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36992 )
Change subject: mb/gigabyte/ga-b75m-d3h: Add ga-b75-d3v as a variant ......................................................................
Patch Set 13:
(1 comment)
https://review.coreboot.org/c/coreboot/+/36992/9/src/mainboard/gigabyte/ga-b... File src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75-d3v/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/36992/9/src/mainboard/gigabyte/ga-b... PS9, Line 20: io 0x62 = 0x230
The superiotool dump when running vendor firmware says so. […]
Overriding removed.
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36992 )
Change subject: mb/gigabyte/ga-b75m-d3h: Add ga-b75-d3v as a variant ......................................................................
Patch Set 13: Code-Review+2
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/36992 )
Change subject: mb/gigabyte/ga-b75m-d3h: Add ga-b75-d3v as a variant ......................................................................
mb/gigabyte/ga-b75m-d3h: Add ga-b75-d3v as a variant
It is an ATX board similar to existing ga-b75* boards. The major difference is the configuration of pci-e ports on PCH, and on-board pci-e NIC. (see below)
Tested: - CPU i5 3570T - Slotted DIMM 8GiB*4 from Kingston - usb2 and usb3 - pci and pci-e ports - sata - Sound - S3 - AR8161 NIC connected to 1c.2 with mac address burnt in efuse - libgfxinit-based graphic init - NVRAM options for North and South bridges - tpm 1.2 on lpc (similar to ga-b75m-d3h) - Linux 4.19.67-2 within Debian GNU/Linux stable, loaded from SeaBIOS.
Change-Id: I1a969880e4da02abf8ba73aac60ee1296fe0abf2 Signed-off-by: Bill XIE persmule@hardenedlinux.org Reviewed-on: https://review.coreboot.org/c/coreboot/+/36992 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Arthur Heymans arthur@aheymans.xyz --- M src/mainboard/gigabyte/ga-b75m-d3h/Kconfig M src/mainboard/gigabyte/ga-b75m-d3h/Kconfig.name A src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75-d3v/board_info.txt A src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75-d3v/gma-mainboard.ads A src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75-d3v/gpio.c A src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75-d3v/include/variant/hda_verb.h A src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75-d3v/overridetree.cb 7 files changed, 313 insertions(+), 2 deletions(-)
Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved
diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/Kconfig b/src/mainboard/gigabyte/ga-b75m-d3h/Kconfig index 64d9cc5..1ad68f4 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/Kconfig +++ b/src/mainboard/gigabyte/ga-b75m-d3h/Kconfig @@ -1,4 +1,4 @@ -if BOARD_GIGABYTE_GA_B75M_D3H || BOARD_GIGABYTE_GA_B75M_D3V +if BOARD_GIGABYTE_GA_B75M_D3H || BOARD_GIGABYTE_GA_B75M_D3V || BOARD_GIGABYTE_GA_B75_D3V
config BOARD_SPECIFIC_OPTIONS def_bool y @@ -34,11 +34,17 @@ string default "ga-b75m-d3h" if BOARD_GIGABYTE_GA_B75M_D3H default "ga-b75m-d3v" if BOARD_GIGABYTE_GA_B75M_D3V + default "ga-b75-d3v" if BOARD_GIGABYTE_GA_B75_D3V
config MAINBOARD_PART_NUMBER string default "GA-B75M-D3H" if BOARD_GIGABYTE_GA_B75M_D3H default "GA-B75M-D3V" if BOARD_GIGABYTE_GA_B75M_D3V + default "GA-B75-D3V" if BOARD_GIGABYTE_GA_B75_D3V + +config OVERRIDE_DEVICETREE + string + default "variants/$(CONFIG_VARIANT_DIR)/overridetree.cb" if BOARD_GIGABYTE_GA_B75_D3V
config MAX_CPUS int @@ -49,4 +55,4 @@ string default "src/mainboard/$(MAINBOARDDIR)/data.vbt"
-endif # BOARD_GIGABYTE_GA_B75M* +endif # BOARD_GIGABYTE_GA_B75* diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/Kconfig.name b/src/mainboard/gigabyte/ga-b75m-d3h/Kconfig.name index f8fbe54..93f73a5 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/Kconfig.name +++ b/src/mainboard/gigabyte/ga-b75m-d3h/Kconfig.name @@ -3,3 +3,6 @@
config BOARD_GIGABYTE_GA_B75M_D3V bool "GA-B75M-D3V" + +config BOARD_GIGABYTE_GA_B75_D3V + bool "GA-B75-D3V" diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75-d3v/board_info.txt b/src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75-d3v/board_info.txt new file mode 100644 index 0000000..f90483f --- /dev/null +++ b/src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75-d3v/board_info.txt @@ -0,0 +1,7 @@ +Category: desktop +Board URL: https://www.gigabyte.com/Motherboard/GA-B75-D3V-rev-11 +ROM package: SOIC-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: y +Release year: 2012 diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75-d3v/gma-mainboard.ads b/src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75-d3v/gma-mainboard.ads new file mode 100644 index 0000000..416732d --- /dev/null +++ b/src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75-d3v/gma-mainboard.ads @@ -0,0 +1,28 @@ +-- +-- Copyright (C) 2017 Bill XIE persmule@gmail.com +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (HDMI1, + Analog, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75-d3v/gpio.c b/src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75-d3v/gpio.c new file mode 100644 index 0000000..763dfad --- /dev/null +++ b/src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75-d3v/gpio.c @@ -0,0 +1,201 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_NATIVE, + .gpio3 = GPIO_MODE_NATIVE, + .gpio4 = GPIO_MODE_NATIVE, + .gpio5 = GPIO_MODE_NATIVE, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_NATIVE, + .gpio11 = GPIO_MODE_NATIVE, + .gpio12 = GPIO_MODE_GPIO, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_NATIVE, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_GPIO, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_NATIVE, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_OUTPUT, + .gpio12 = GPIO_DIR_OUTPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_OUTPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio19 = GPIO_DIR_INPUT, + .gpio21 = GPIO_DIR_INPUT, + .gpio22 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio29 = GPIO_DIR_INPUT, + .gpio31 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio8 = GPIO_LEVEL_HIGH, + .gpio12 = GPIO_LEVEL_HIGH, + .gpio15 = GPIO_LEVEL_LOW, + .gpio24 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { + .gpio24 = GPIO_RESET_RSMRST, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio13 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_GPIO, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_GPIO, + .gpio37 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_NATIVE, + .gpio45 = GPIO_MODE_NATIVE, + .gpio46 = GPIO_MODE_NATIVE, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_NATIVE, + .gpio51 = GPIO_MODE_NATIVE, + .gpio52 = GPIO_MODE_NATIVE, + .gpio53 = GPIO_MODE_NATIVE, + .gpio54 = GPIO_MODE_NATIVE, + .gpio55 = GPIO_MODE_NATIVE, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_NATIVE, + .gpio61 = GPIO_MODE_NATIVE, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_OUTPUT, + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio35 = GPIO_DIR_OUTPUT, + .gpio36 = GPIO_DIR_INPUT, + .gpio37 = GPIO_DIR_INPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio48 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio32 = GPIO_LEVEL_HIGH, + .gpio33 = GPIO_LEVEL_HIGH, + .gpio35 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_NATIVE, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_NATIVE, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_NATIVE, + .gpio71 = GPIO_MODE_NATIVE, + .gpio72 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_NATIVE, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio72 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75-d3v/include/variant/hda_verb.h b/src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75-d3v/include/variant/hda_verb.h new file mode 100644 index 0000000..76c4ed3 --- /dev/null +++ b/src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75-d3v/include/variant/hda_verb.h @@ -0,0 +1,43 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef GA_B75_D3V_HDA_VERB_H +#define GA_B75_D3V_HDA_VERB_H + +const u32 cim_verb_data[] = { + /* coreboot specific header */ + 0x10ec0887, // Realtek 887 + 0x1458a002, // Subsystem ID + 0x0000000e, // Number of entries + + /* NID 0x01: Subsystem ID. */ + AZALIA_SUBVENDOR(0x2, 0x1458a002), + + /* Pin Widget Verb Table */ + AZALIA_PIN_CFG(0x2, 0x11, 0x99430130), + AZALIA_PIN_CFG(0x2, 0x12, 0x411111f0), + AZALIA_PIN_CFG(0x2, 0x14, 0x01014410), + AZALIA_PIN_CFG(0x2, 0x15, 0x411111f0), + AZALIA_PIN_CFG(0x2, 0x16, 0x411111f0), + AZALIA_PIN_CFG(0x2, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0x2, 0x18, 0x01a19c50), + AZALIA_PIN_CFG(0x2, 0x19, 0x02a19c60), + AZALIA_PIN_CFG(0x2, 0x1a, 0x0181345f), + AZALIA_PIN_CFG(0x2, 0x1b, 0x02214c20), + AZALIA_PIN_CFG(0x2, 0x1c, 0x411111f0), + AZALIA_PIN_CFG(0x2, 0x1d, 0x4004c601), + AZALIA_PIN_CFG(0x2, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(0x2, 0x1f, 0x411111f0), +}; + +#endif diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75-d3v/overridetree.cb b/src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75-d3v/overridetree.cb new file mode 100644 index 0000000..2fd3cd5 --- /dev/null +++ b/src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75-d3v/overridetree.cb @@ -0,0 +1,23 @@ +chip northbridge/intel/sandybridge + device domain 0 on + chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH + device pci 16.0 off end # Management Engine Interface 1 + register "xhci_overcurrent_mapping" = "0x00000c03" + device pci 1c.1 on end # PCIe Port #2 + device pci 1c.2 on + device pci 00.0 on # PCI 1969:1091 + subsystemid 0x1458 0xe000 + end + end # PCIe Port #3 + device pci 1c.3 on end # PCIe Port #4 + device pci 1c.4 on end # PCIe Port #5 + device pci 1f.0 on # ISA/LPC bridge + subsystemid 0x1458 0x5001 + chip superio/ite/it8728f + device pnp 2e.2 off end # COM2 + device pnp 2e.3 off end # LPT + end + end + end + end +end
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Angel Pons (Code Review) -
Arthur Heymans (Code Review)
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Bill XIE (Code Review)
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Patrick Georgi (Code Review)
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Paul Menzel (Code Review)