Attention is currently required from: Bora Guvendik, Anil Kumar K, Furquan Shaikh, Tim Wawrzynczak, Sugnan Prabhu S, Bernardo Perez Priego, Ronak Kanabar. Maulik V Vaghela has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52270 )
Change subject: mb/intel/adlrvp: Program CPU PCIE RP GPIOs in early GPIO ......................................................................
Patch Set 11:
(1 comment)
File src/mainboard/intel/adlrvp/early_gpio.c:
https://review.coreboot.org/c/coreboot/+/52270/comment/d345a68c_1cec178b PS10, Line 20: PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_0, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_1, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_3, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_2, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_4, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_5, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_6, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_7, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_8, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_9, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_10, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_11, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_12, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_13, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_14, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_15, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_64, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_65, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_66, NONE, DEEP, NF1), : PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_67, NONE, DEEP, NF1),
May I ask where these mappings come from? It's slightly curious that there's 16 in a row then a big […]
Hi Tim, The mapping is like this for each port because of Tx-Rx lines of PCI port. We have 0-15 as Tx and 64-67 as Rx for port 0 and thus we configure it in that sequence.
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Maulik V Vaghela (Code Review)