[XS] Change in coreboot[master]: soc/intel/xeon_sp/spr: Fix memory max capacity per processor

[Ziang Wang (Code Review)]

Ziang Wang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/75740?usp=email )

Change subject: soc/intel/xeon_sp/spr: Fix memory max capacity per processor
......................................................................

soc/intel/xeon_sp/spr: Fix memory max capacity per processor

The capacity shall be 6*TiB per processor.

Change-Id: Ieb892d3b148291b35808d634d63b58b90d456767
Signed-off-by: wanghao11 
Signed-off-by: Ziang Wang 
---
M src/soc/intel/xeon_sp/spr/romstage.c
1 file changed, 6 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/75740/1

diff --git a/src/soc/intel/xeon_sp/spr/romstage.c b/src/soc/intel/xeon_sp/spr/romstage.c
index fef4d94..62b6212 100644
--- a/src/soc/intel/xeon_sp/spr/romstage.c
+++ b/src/soc/intel/xeon_sp/spr/romstage.c
@@ -271,8 +271,12 @@
    	return;
    }
    memset(mem_info, 0, sizeof(*mem_info));
-	/* According to EDS doc#611488, it's 4 TB per processor. */
-	mem_info->max_capacity_mib = 4 * MiB * CONFIG_MAX_SOCKET;
+	/*
+	 * According to EDS doc#611488, it's 6 TB per processor
+	 * Max Capacity: (x8 256 GB 16 Gb 3DS DDR5) and (x8 512 GB Intel® Optane™
+	 * Persistent Memory 300 Series mapped as memory) per Socket
+	 */
+	mem_info->max_capacity_mib = 6 * MiB * CONFIG_MAX_SOCKET;
    mem_info->number_of_devices = CONFIG_DIMM_MAX;
    mem_info->ecc_type = get_error_correction_type(hob->RasModesEnabled);
    dimm_max = ARRAY_SIZE(mem_info->dimm);