Change in coreboot[master]: src/soc/tigerlake: Enabled D3ColdEnable in fsp_params

[Caveh Jalali (Code Review)]

Hello build bot (Jenkins), Wonkyu Kim, John Zhao, Nick Vaccaro, Srinidhi N Kaushik, Patrick Rudolph, Divya S Sasidharan,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/39369

to look at the new patch set (#3).

Change subject: src/soc/tigerlake: Enabled D3ColdEnable in fsp_params
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src/soc/tigerlake: Enabled D3ColdEnable in fsp_params

Tcss Thunderbolt is D3-cold capable and is recommended.
This enables the D3ColdEnable feature for TCSS Thunderbolt
when s0ix is enabled.

BUG=b:146624360,b:150912117
BRANCH=none
TEST="Build and Boot on Volteer"

Change-Id: If2b1b0b3b50cd8a7b2f974579dc281bcd65c243a
Signed-off-by: John Zhao 
Reviewed-on: https://chrome-internal-review.googlesource.com/c/chromeos/third_party/coreb...
Reviewed-by: Caveh Jalali 
Reviewed-by: Nick Vaccaro 
Reviewed-by: Wonkyu Kim 
Tested-by: Divya S Sasidharan 
Commit-Queue: Caveh Jalali 
---
M src/soc/intel/tigerlake/fsp_params_tgl.c
M src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h
2 files changed, 7 insertions(+), 6 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/39369/3