Paul Menzel has posted comments on this change by Vince Liu. ( https://review.coreboot.org/c/coreboot/+/86538?usp=email )
Change subject: soc/mediatek/mt8189: Reduce bootblock size by separating SPI NOR GPIOs
......................................................................
Patch Set 4:
(1 comment)
File src/soc/mediatek/mt8189/gpio.c:
https://review.coreboot.org/c/coreboot/+/86538/comment/117311a6_083030fe?usp... :
PS4, Line 23: [SPI_NOR_CK] = { 0x10, 12, 3, },
: [SPI_NOR_CS] = { 0x10, 27, 3, },
: [SPI_NOR_IO0] = { 0x10, 15, 3, },
: [SPI_NOR_IO1] = { 0x10, 18, 3, },
: [SPI_NOR_IO2] = { 0x10, 21, 3, },
: [SPI_NOR_IO3] = { 0x10, 24, 3, },
A comment would have been nice, that to compare the tables SPI_NOR_GPIO_BASE has to be added.
--
To view, visit
https://review.coreboot.org/c/coreboot/+/86538?usp=email
To unsubscribe, or for help writing mail filters, visit
https://review.coreboot.org/settings?usp=email
Gerrit-MessageType: comment
Gerrit-Project: coreboot
Gerrit-Branch: main
Gerrit-Change-Id: If7e8e5c7db59b5f181db14f6e66df2f333dbb6d4
Gerrit-Change-Number: 86538
Gerrit-PatchSet: 4
Gerrit-Owner: Vince Liu
vince-wl.liu@mediatek.com
Gerrit-Reviewer: Hung-Te Lin
hungte@chromium.org
Gerrit-Reviewer: Yidi Lin
yidilin@google.com
Gerrit-Reviewer: Yu-Ping Wu
yupingso@google.com
Gerrit-Reviewer: build bot (Jenkins)
no-reply@coreboot.org
Gerrit-CC: 9elements QA
hardwaretestrobot@gmail.com
Gerrit-CC: Paul Menzel
paulepanter@mailbox.org
Gerrit-Comment-Date: Tue, 25 Feb 2025 15:42:27 +0000
Gerrit-HasComments: Yes
Gerrit-Has-Labels: No