Change in coreboot[master]: nb/intel/gm45/gm45.h: Move includes to top of file

[HAOUAS Elyes (Code Review)]

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50833 )

Change subject: nb/intel/gm45/gm45.h: Move includes to top of file
......................................................................

nb/intel/gm45/gm45.h: Move includes to top of file

Change-Id: If1bb2c7e5cead5761f3100ec9ee4681f37e7a5cc
Signed-off-by: Elyes HAOUAS 
---
M src/northbridge/intel/gm45/gm45.h
1 file changed, 4 insertions(+), 6 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/50833/1

diff --git a/src/northbridge/intel/gm45/gm45.h b/src/northbridge/intel/gm45/gm45.h
index b6e7c2f..5f481de 100644
--- a/src/northbridge/intel/gm45/gm45.h
+++ b/src/northbridge/intel/gm45/gm45.h
@@ -3,8 +3,12 @@
 #ifndef __NORTHBRIDGE_INTEL_GM45_GM45_H__
 #define __NORTHBRIDGE_INTEL_GM45_GM45_H__

+#include <device/device.h>
+#include <northbridge/intel/common/fixed_bars.h>
 #include <stdint.h>

+#include "memmap.h"
+
 typedef enum {
    FSB_CLOCK_1067MHz = 0,
    FSB_CLOCK_800MHz  = 1,
@@ -164,8 +168,6 @@
 #define CMOS_READ_TRAINING	0x80 /* 16 bytes */
 #define CMOS_WRITE_TRAINING	0x90 /* 16 bytes (could be reduced to 10 bytes) */

-#include "memmap.h"
-
 /*
  * D0:F0
  */
@@ -218,8 +220,6 @@
  * MCHBAR
  */

-#include <northbridge/intel/common/fixed_bars.h>
-
 #define HPLLVCO_MCHBAR		0x0c0f

#define PMSTS_MCHBAR		0x0f14	/* Self refresh channel status */
@@ -434,8 +434,6 @@
 int get_blc_values(const struct blc_pwm_t **entries);
 u16 get_blc_pwm_freq_value(const char *edid_ascii_string);

-#include <device/device.h>
-
 struct acpi_rsdp;
 unsigned long northbridge_write_acpi_tables(const struct device *device, unsigned long start,
    					struct acpi_rsdp *rsdp);