Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/62096 )
Change subject: device: Add more HyperTransport definitions ......................................................................
device: Add more HyperTransport definitions
Signed-off-by: Michał Żygowski michal.zygowski@3mdeb.com Change-Id: I60e2bdd977627d72ccaaf9d3fe4e37bb12fb8b17 --- A src/include/device/hypertransport.h M src/include/device/pci_def.h 2 files changed, 182 insertions(+), 7 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/62096/1
diff --git a/src/include/device/hypertransport.h b/src/include/device/hypertransport.h new file mode 100644 index 0000000..ddd8b04 --- /dev/null +++ b/src/include/device/hypertransport.h @@ -0,0 +1,161 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef DEVICE_HYPERTRANSPORT_H +#define DEVICE_HYPERTRANSPORT_H + +/* From HyperTransport I/O Link Specification Revision 3.10 */ + +/* HT Capability Command Register (offset 0x2) */ +/* HT Slave/Primary */ +#define HT_PRIMARY_BASE_UNIT_ID_MASK 0x1f +#define HT_PRIMARY_BASE_UNIT_ID_OFFSET 0 +#define HT_PRIMARY_UNIT_COUNT_MASK 0x1f +#define HT_PRIMARY_UNIT_COUNT_OFFSET 5 +#define HT_PRIMARY_DEF_DIRECTION BIT(11) + +/* HT Host/Secondary */ +#define HT_SECONDARY_WARM_RESET BIT(0) +#define HT_SECONDARY_DOUBLE_ENDED BIT(1) +#define HT_SECONDARY_DEV_NUMBER_MASK 0x1f +#define HT_SECONDARY_DEV_NUMBER_OFFSET 2 +#define HT_SECONDARY_CHAIN_SIDE BIT(7) +#define HT_SECONDARY_HOST_SIDE BIT(8) +#define HT_SECONDARY_EOC_ERROR BIT(11) + +/* Common Comand Register Bits */ +#define HT_CMD_MASTER_OR_SLAVE BIT(10) +#define HT_CMD_DROP_ON_UNINITTED_LINK BIT(12) +#define HT_CMD_CAP_TYPE_MASK 0x7 +#define HT_CMD_CAP_OFFSET 13 +#define HT_CMD_CAP_PRIMARY 0 +#define HT_CMD_CAP_SECONDARY 1 + +/* HT Capability Link Control Register (offsets 0x4 and 0x8) */ +#define HT_LINK_CTRL_SRC_ID_EN BIT(0) +#define HT_LINK_CTRL_CRC_FLOOD_EN BIT(1) +#define HT_LINK_CTRL_CRC_START_TEST BIT(2) +#define HT_LINK_CTRL_CRC_FORCE_ERR BIT(3) +#define HT_LINK_CTRL_LINK_FAIL BIT(4) +#define HT_LINK_CTRL_INIT_COMPLETE BIT(5) +#define HT_LINK_CTRL_END_OF_CHAIN BIT(6) +#define HT_LINK_CTRL_TRANSMITTER_OFF BIT(7) +#define HT_LINK_CTRL_CRC_UNRECOV_ERR BIT(8) /* only when link is in retry mode */ +#define HT_LINK_CTRL_CRC_ERR_MASK 0xf +#define HT_LINK_CTRL_CRC_ERR_OFFSET 8 +#define HT_LINK_CTRL_ISOC_EN BIT(12) +#define HT_LINK_CTRL_LS_EN BIT(13) +#define HT_LINK_CTRL_EXT_CTL BIT(14) +#define HT_LINK_CTRL_64B_ADDR_EN BIT(15) + +/* HT Capability Link Configuration Register (offsets 0x6 and 0xa) */ +#define HT_LINK_CONF_WIDTH_2 4 +#define HT_LINK_CONF_WIDTH_4 5 +#define HT_LINK_CONF_WIDTH_8 0 +#define HT_LINK_CONF_WIDTH_16 1 +#define HT_LINK_CONF_WIDTH_32 3 +#define HT_LINK_CONF_LINK_NOT_CONNECTED 7 + +#define HT_LINK_CONF_MAX_LINK_WIDTH_IN_MASK 0x7 +#define HT_LINK_CONF_MAX_LINK_WIDTH_IN_OFFSET 0 +#define HT_LINK_CONF_DWORD_FLOW_CTRL_IN BIT(3) +#define HT_LINK_CONF_MAX_LINK_WIDTH_OUT_MASK 0x7 +#define HT_LINK_CONF_MAX_LINK_WIDTH_OUT_OFFSET 4 +#define HT_LINK_CONF_DWORD_FLOW_CTRL_OUT BIT(7) +#define HT_LINK_CONF_LINK_WIDTH_IN_MASK 0x7 +#define HT_LINK_CONF_LINK_WIDTH_IN_OFFSET 8 +#define HT_LINK_CONF_DWORD_FLOW_CTRL_IN_EN BIT(11) +#define HT_LINK_CONF_LINK_WIDTH_OUT_MASK 0x7 +#define HT_LINK_CONF_LINK_WIDTH_OUT_OFFSET 12 +#define HT_LINK_CONF_DWORD_FLOW_CTRL_OUT_EN BIT(15) + +/* HT Capability Revision ID Register (offsets 0x8 and 0xc) */ +/* Byte register, BSD format: Major Rev [7:5], Minor Rev [4:0] */ +#define HT_REV_MINOR_OFFSET 0 +#define HT_REV_MINOR_MASK 0x1f +#define HT_REV_MAJOR_OFFSET 5 +#define HT_REV_MAJOR_MASK 0x7 + +/* HT Capability Frequency Register (offsets 0x9 or 0xd and 0x11 (bits 3:0)) */ +#define HT_LINK_FREQ_200MHZ 0 +#define HT_LINK_FREQ_300MHZ 1 +#define HT_LINK_FREQ_400MHZ 2 +#define HT_LINK_FREQ_500MHZ 3 +#define HT_LINK_FREQ_600MHZ 4 +#define HT_LINK_FREQ_800MHZ 5 +#define HT_LINK_FREQ_1000MHZ 6 +#define HT_LINK_FREQ_1200MHZ 7 +#define HT_LINK_FREQ_1400MHZ 8 +#define HT_LINK_FREQ_1600MHZ 9 +#define HT_LINK_FREQ_1800MHZ 10 +#define HT_LINK_FREQ_2000MHZ 11 +#define HT_LINK_FREQ_2200MHZ 12 +#define HT_LINK_FREQ_2400MHZ 13 +#define HT_LINK_FREQ_2600MHZ 14 +#define HT_LINK_FREQ_VENDOR 15 /* AMD defines this to be 100Mhz */ +#define HT_LINK_FREQ_RESERVED 16 +#define HT_LINK_FREQ_2800MHZ 17 +#define HT_LINK_FREQ_3000MHZ 18 +#define HT_LINK_FREQ_3200MHZ 19 + +/* HT Capability Link Error Register (offsets 0x9 or 0xd and 0x11 (bits 7:4)) */ + +#define HT_LINK_PROTOCOL_ERR BIT(4) +#define HT_LINK_OVERFLOW_ERR BIT(5) +#define HT_LINK_END_OF_CHAIN_ERR BIT(6) +#define HT_LINK_CTL_TIMEOUT BIT(7) + +/* HT Capability Frequency Capability Register (offsets 0xa or 0xe and 0x12) */ + +/* Each bit set in this register indicates suport for the frequency from the + * Frequency Register (offsets 0x9 or 0xd and 0x11 (bits 3:0)). I.e. bit 0 + * indicates 200MHz support (always set), bit1 300MHz up to bit15 vendor-specific + * frequencies. + */ +#define HT_LINK_FREQ_CAP_200MHZ BIT(0) +#define HT_LINK_FREQ_CAP_300MHZ BIT(1) +#define HT_LINK_FREQ_CAP_400MHZ BIT(2) +#define HT_LINK_FREQ_CAP_500MHZ BIT(3) +#define HT_LINK_FREQ_CAP_600MHZ BIT(4) +#define HT_LINK_FREQ_CAP_800MHZ BIT(5) +#define HT_LINK_FREQ_CAP_1000MHZ BIT(6) +#define HT_LINK_FREQ_CAP_1200MHZ BIT(7) +#define HT_LINK_FREQ_CAP_1400MHZ BIT(8) +#define HT_LINK_FREQ_CAP_1600MHZ BIT(9) +#define HT_LINK_FREQ_CAP_1800MHZ BIT(10) +#define HT_LINK_FREQ_CAP_2000MHZ BIT(11) +#define HT_LINK_FREQ_CAP_2200MHZ BIT(12) +#define HT_LINK_FREQ_CAP_2400MHZ BIT(13) +#define HT_LINK_FREQ_CAP_2600MHZ BIT(14) +#define HT_LINK_FREQ_CAP_VENDOR BIT(15) /* AMD defines this to be 100Mhz */ + +/* HT Capability Feature Register (offsets 0xc or 0x10) */ +#define HT_FEATURE_CAP_ISOC_FLOW_CTL_MODE BIT(0) +#define HT_FEATURE_CAP_LDTSTOP BIT(1) +#define HT_FEATURE_CAP_CRC_TEST_MODE BIT(2) +#define HT_FEATURE_CAP_EXT_CTL_TIME_REQUIRED BIT(3) +#define HT_FEATURE_CAP_64B_ADRESSING BIT(4) +#define HT_FEATURE_CAP_UNIT_ID_REORDER_DISABLE BIT(5) +#define HT_FEATURE_CAP_SRC_ID_EXTENSION BIT(6) +#define HT_FEATURE_CAP_RESERVED BIT(7) +#define HT_FEATURE_CAP_EXTENDED_REG_SET BIT(8) /* Host only */ +#define HT_FEATURE_CAP_UPSTREAM_CONF_EN BIT(9) /* Host only */ + +/* HT Capability Error Handling Register (offsets 0x12 or 0x16) */ +#define HT_ERROR_HANDLING_PROTOCOL_FLOOD_EN BIT(0) +#define HT_ERROR_HANDLING_OVERFLOW_FLOOD_EN BIT(1) +#define HT_ERROR_HANDLING_PROTOCOL_FATAL_EN BIT(2) +#define HT_ERROR_HANDLING_OVERFLOW_FATAL_EN BIT(3) +#define HT_ERROR_HANDLING_EOC_FATAL_EN BIT(4) +#define HT_ERROR_HANDLING_RESPONSE_FATAL_EN BIT(5) +#define HT_ERROR_HANDLING_CRC_FATAL_EN BIT(6) +#define HT_ERROR_HANDLING_SERR_FATAL_EN BIT(7) +#define HT_ERROR_HANDLING_CHAIN_FAIL BIT(8) +#define HT_ERROR_HANDLING_RESPONSE_ERR BIT(9) +#define HT_ERROR_HANDLING_PROTOCOL_NONFATAL_EN BIT(10) +#define HT_ERROR_HANDLING_OVERFLOW_NONFATAL_EN BIT(11) +#define HT_ERROR_HANDLING_EOC_NONFATAL_EN BIT(12) +#define HT_ERROR_HANDLING_RESPONSE_NONFATAL_EN BIT(13) +#define HT_ERROR_HANDLING_CRC_NONFATAL_EN BIT(14) +#define HT_ERROR_HANDLING_SERR_NONFATAL_EN BIT(15) + +#endif /* DEVICE_HYPERTRANSPORT_H */ diff --git a/src/include/device/pci_def.h b/src/include/device/pci_def.h index 0611436..07cfb99 100644 --- a/src/include/device/pci_def.h +++ b/src/include/device/pci_def.h @@ -207,19 +207,33 @@
/* Hypertransport Registers */ #define PCI_HT_CAP_SIZEOF 4 -#define PCI_HT_CAP_HOST_CTRL 4 /* Host link control */ -#define PCI_HT_CAP_HOST_WIDTH 6 /* width value & capability */ +#define PCI_HT_CAP_HOST_CMD 0x02 /* Host link command */ +#define PCI_HT_CAP_HOST_CTRL 0x04 /* Host link control */ +#define PCI_HT_CAP_HOST_WIDTH 0x06 /* width value & capability */ +#define PCI_HT_CAP_HOST_REV_ID 0x08 /* Revision ID */ #define PCI_HT_CAP_HOST_FREQ 0x09 /* Host frequency */ #define PCI_HT_CAP_HOST_FREQ_CAP 0x0a /* Host Frequency capability */ -#define PCI_HT_CAP_SLAVE_CTRL0 4 /* link control */ -#define PCI_HT_CAP_SLAVE_CTRL1 8 /* link control to */ -#define PCI_HT_CAP_SLAVE_WIDTH0 6 /* width value & capability */ +#define PCI_HT_CAP_HOST_FEAT 0x0c /* Host feature */ +#define PCI_HT_CAP_HOST_LINK_ENUM 0x10 /* Host Link Enumeration Scratchpad */ +#define PCI_HT_CAP_HOST_ERR_HANDL 0x12 /* Host Error Handling */ +#define PCI_HT_CAP_HOST_MEM_BASE 0x14 /* Host Mem Base Upper */ +#define PCI_HT_CAP_HOST_MEM_LIMIT 0x15 /* Host Mem Limit Upper */ +#define PCI_HT_CAP_SLAVE_CMD 0x02 /* Slave link command */ +#define PCI_HT_CAP_SLAVE_CTRL0 0x04 /* link control */ +#define PCI_HT_CAP_SLAVE_CTRL1 0x08 /* link control to */ +#define PCI_HT_CAP_SLAVE_WIDTH0 0x06 /* width value & capability */ #define PCI_HT_CAP_SLAVE_WIDTH1 0x0a /* width value & capability to */ +#define PCI_HT_CAP_SLAVE_REV_ID 0x0c /* Slave Revision ID */ #define PCI_HT_CAP_SLAVE_FREQ0 0x0d /* Slave frequency from */ -#define PCI_HT_CAP_SLAVE_FREQ1 0x011 /* Slave frequency to */ +#define PCI_HT_CAP_SLAVE_FEAT 0x10 /* Slave feature */ +#define PCI_HT_CAP_SLAVE_FREQ1 0x11 /* Slave frequency to */ #define PCI_HT_CAP_SLAVE_FREQ_CAP0 0x0e /* Frequency capability from */ #define PCI_HT_CAP_SLAVE_FREQ_CAP1 0x12 /* Frequency capability to */ -#define PCI_HT_CAP_SLAVE_LINK_ENUM 0x14 /* Link Enumeration Scratchpad */ +#define PCI_HT_CAP_SLAVE_LINK_ENUM 0x14 /* Slave Link Enumeration Scratchpad */ +#define PCI_HT_CAP_SLAVE_ERR_HANDL 0x16 /* Slave Error Handling */ +#define PCI_HT_CAP_SLAVE_MEM_BASE 0x18 /* Slave Mem Base Upper */ +#define PCI_HT_CAP_SLAVE_MEM_LIMIT 0x19 /* Slave Mem Limit Upper */ +#define PCI_HT_CAP_SLAVE_BUS_NUM 0x20 /* Slave bus Number */
/* Power Management Registers */
-
Michał Żygowski (Code Review)