Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/84161?usp=email )
Change subject: tree: Use boolean for dptf_enable ......................................................................
tree: Use boolean for dptf_enable
Change-Id: Ic6e578199e7e4ca3a014eecb1eb7a4d9d24893b8 Signed-off-by: Elyes Haouas ehaouas@noos.fr --- M src/mainboard/51nb/x210/devicetree.cb M src/mainboard/aoostar/wtr_r1/devicetree.cb M src/mainboard/asrock/h110m/devicetree.cb M src/mainboard/facebook/monolith/devicetree.cb M src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb M src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb M src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb M src/mainboard/google/brya/variants/baseboard/hades/devicetree.cb M src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb M src/mainboard/google/brya/variants/orisa/overridetree.cb M src/mainboard/google/brya/variants/trulo/overridetree.cb M src/mainboard/google/dedede/variants/baseboard/devicetree.cb M src/mainboard/google/drallion/variants/drallion/devicetree.cb M src/mainboard/google/eve/devicetree.cb M src/mainboard/google/fizz/variants/baseboard/devicetree.cb M src/mainboard/google/glados/devicetree.cb M src/mainboard/google/hatch/variants/baseboard/devicetree.cb M src/mainboard/google/octopus/variants/baseboard/devicetree.cb M src/mainboard/google/poppy/variants/atlas/devicetree.cb M src/mainboard/google/poppy/variants/baseboard/devicetree.cb M src/mainboard/google/poppy/variants/nami/devicetree.cb M src/mainboard/google/poppy/variants/nautilus/devicetree.cb M src/mainboard/google/poppy/variants/nocturne/devicetree.cb M src/mainboard/google/poppy/variants/rammus/devicetree.cb M src/mainboard/google/poppy/variants/soraka/devicetree.cb M src/mainboard/google/puff/variants/baseboard/devicetree.cb M src/mainboard/google/reef/variants/baseboard/devicetree.cb M src/mainboard/google/reef/variants/coral/devicetree.cb M src/mainboard/google/reef/variants/pyro/devicetree.cb M src/mainboard/google/reef/variants/sand/devicetree.cb M src/mainboard/google/reef/variants/snappy/devicetree.cb M src/mainboard/google/rex/variants/baseboard/ovis/devicetree.cb M src/mainboard/google/rex/variants/baseboard/ovis/devicetree_pre_prod.cb M src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb M src/mainboard/google/rex/variants/baseboard/rex/devicetree_pre_prod.cb M src/mainboard/google/sarien/variants/arcada/devicetree.cb M src/mainboard/google/sarien/variants/sarien/devicetree.cb M src/mainboard/google/volteer/variants/baseboard/devicetree.cb M src/mainboard/intel/adlrvp/devicetree.cb M src/mainboard/intel/adlrvp/devicetree_n.cb M src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb M src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb M src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb M src/mainboard/intel/kunimitsu/devicetree.cb M src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb M src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb M src/mainboard/kontron/mal10/variants/mal10/devicetree.cb M src/mainboard/libretrend/lt1000/devicetree.cb M src/mainboard/protectli/vault_kbl/devicetree.cb M src/mainboard/purism/librem_skl/devicetree.cb M src/mainboard/razer/blade_stealth_kbl/devicetree.cb M src/soc/intel/elkhartlake/chip.h M src/soc/intel/pantherlake/chip.h M src/soc/intel/tigerlake/chip.h 55 files changed, 55 insertions(+), 55 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/84161/1
diff --git a/src/mainboard/51nb/x210/devicetree.cb b/src/mainboard/51nb/x210/devicetree.cb index e489e25..d3f50ef 100644 --- a/src/mainboard/51nb/x210/devicetree.cb +++ b/src/mainboard/51nb/x210/devicetree.cb @@ -27,7 +27,7 @@ register "gpe0_dw2" = "GPP_E"
# Disable DPTF - register "dptf_enable" = "0" + register "dptf_enable" = "false"
# FSP Configuration register "DspEnable" = "0" diff --git a/src/mainboard/aoostar/wtr_r1/devicetree.cb b/src/mainboard/aoostar/wtr_r1/devicetree.cb index a802cca..18109c8 100644 --- a/src/mainboard/aoostar/wtr_r1/devicetree.cb +++ b/src/mainboard/aoostar/wtr_r1/devicetree.cb @@ -12,7 +12,7 @@
register "sagv" = "SaGv_Enabled"
- register "dptf_enable" = "1" + register "dptf_enable" = "true"
register "s0ix_enable" = "true"
diff --git a/src/mainboard/asrock/h110m/devicetree.cb b/src/mainboard/asrock/h110m/devicetree.cb index 59e297c..d999973 100644 --- a/src/mainboard/asrock/h110m/devicetree.cb +++ b/src/mainboard/asrock/h110m/devicetree.cb @@ -15,7 +15,7 @@ register "gpe0_dw2" = "GPP_E"
# Enable DPTF - register "dptf_enable" = "1" + register "dptf_enable" = "true"
# FSP Configuration register "PrimaryDisplay" = "Display_PEG" diff --git a/src/mainboard/facebook/monolith/devicetree.cb b/src/mainboard/facebook/monolith/devicetree.cb index ad735ed..14ac280 100644 --- a/src/mainboard/facebook/monolith/devicetree.cb +++ b/src/mainboard/facebook/monolith/devicetree.cb @@ -22,7 +22,7 @@ register "eist_enable" = "true"
# DPTF - register "dptf_enable" = "1" + register "dptf_enable" = "true"
# FSP Configuration register "ScsEmmcHs400Enabled" = "1" diff --git a/src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb b/src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb index b900af1..ce39527 100644 --- a/src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb +++ b/src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb @@ -25,7 +25,7 @@ register "disable_c1_state_auto_demotion" = "1"
# DPTF enable - register "dptf_enable" = "1" + register "dptf_enable" = "true"
register "tcc_offset" = "10" # TCC of 90
diff --git a/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb index 2ba54bc..b583cc8 100644 --- a/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb @@ -18,7 +18,7 @@ register "s0ix_enable" = "true"
# DPTF enable - register "dptf_enable" = "1" + register "dptf_enable" = "true"
register "tcc_offset" = "10" # TCC of 90
diff --git a/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb index e07cf2a..397e0f5 100644 --- a/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb @@ -19,7 +19,7 @@ register "disable_package_c_state_demotion" = "1"
# DPTF enable - register "dptf_enable" = "1" + register "dptf_enable" = "true"
register "tcc_offset" = "10" # TCC of 90
diff --git a/src/mainboard/google/brya/variants/baseboard/hades/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/hades/devicetree.cb index f91b088..a24b657 100644 --- a/src/mainboard/google/brya/variants/baseboard/hades/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/hades/devicetree.cb @@ -15,7 +15,7 @@ register "s0ix_enable" = "true"
# DPTF enable - register "dptf_enable" = "1" + register "dptf_enable" = "true"
register "tcc_offset" = "10" # TCC of 90
diff --git a/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb index 3d28ed3..d2518d6 100644 --- a/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb @@ -32,7 +32,7 @@ register "s0ix_enable" = "true"
# DPTF enable - register "dptf_enable" = "1" + register "dptf_enable" = "true"
register "tcc_offset" = "10" # TCC of 90
diff --git a/src/mainboard/google/brya/variants/orisa/overridetree.cb b/src/mainboard/google/brya/variants/orisa/overridetree.cb index ad5b943..f3ad232 100644 --- a/src/mainboard/google/brya/variants/orisa/overridetree.cb +++ b/src/mainboard/google/brya/variants/orisa/overridetree.cb @@ -27,7 +27,7 @@ register "s0ix_enable" = "true"
# DPTF enable - register "dptf_enable" = "1" + register "dptf_enable" = "true"
register "tcc_offset" = "10" # TCC of 90
diff --git a/src/mainboard/google/brya/variants/trulo/overridetree.cb b/src/mainboard/google/brya/variants/trulo/overridetree.cb index 868342b..6fb91ff 100644 --- a/src/mainboard/google/brya/variants/trulo/overridetree.cb +++ b/src/mainboard/google/brya/variants/trulo/overridetree.cb @@ -27,7 +27,7 @@ register "s0ix_enable" = "true"
# DPTF enable - register "dptf_enable" = "1" + register "dptf_enable" = "true"
register "tcc_offset" = "10" # TCC of 90
diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb index cc2b66d..2b55e7c 100644 --- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb @@ -159,7 +159,7 @@ register "DdiPortCDdc" = "1"
# Enable DPTF - register "dptf_enable" = "1" + register "dptf_enable" = "true"
# Power limit config register "power_limits_config[JSL_N4500_6W_CORE]" = "{ diff --git a/src/mainboard/google/drallion/variants/drallion/devicetree.cb b/src/mainboard/google/drallion/variants/drallion/devicetree.cb index 7238a06..23fc46d 100644 --- a/src/mainboard/google/drallion/variants/drallion/devicetree.cb +++ b/src/mainboard/google/drallion/variants/drallion/devicetree.cb @@ -40,7 +40,7 @@ register "PchUsb2PhySusPgDisable" = "1"
register "s0ix_enable" = "true" - register "dptf_enable" = "1" + register "dptf_enable" = "true" register "power_limits_config" = "{ .tdp_pl1_override = 25, .tdp_pl2_override = 51, diff --git a/src/mainboard/google/eve/devicetree.cb b/src/mainboard/google/eve/devicetree.cb index c0779c6..e959607 100644 --- a/src/mainboard/google/eve/devicetree.cb +++ b/src/mainboard/google/eve/devicetree.cb @@ -184,7 +184,7 @@ [PchSerialIoIndexUart2] = PchSerialIoSkipInit, }"
- register "dptf_enable" = "1" + register "dptf_enable" = "true" register "power_limits_config" = "{ .tdp_pl1_override = 7, .tdp_pl2_override = 15, diff --git a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb index 2976deb..a00d01b 100644 --- a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb @@ -53,7 +53,7 @@ register "gpe0_dw2" = "GPP_E"
# Enable DPTF - register "dptf_enable" = "1" + register "dptf_enable" = "true"
# Enable S0ix register "s0ix_enable" = true diff --git a/src/mainboard/google/glados/devicetree.cb b/src/mainboard/google/glados/devicetree.cb index 2d2e13c..005852d 100644 --- a/src/mainboard/google/glados/devicetree.cb +++ b/src/mainboard/google/glados/devicetree.cb @@ -28,7 +28,7 @@ register "gpe0_dw2" = "GPP_E"
# Enable DPTF - register "dptf_enable" = "1" + register "dptf_enable" = "true"
# FSP Configuration register "DspEnable" = "1" diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb index 8c33f02..0b4558b 100644 --- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb @@ -30,7 +30,7 @@ # Enable S0ix register "s0ix_enable" = "true" # Enable DPTF - register "dptf_enable" = "1" + register "dptf_enable" = "true" register "power_limits_config" = "{ .tdp_pl1_override = 15, .tdp_pl2_override = 64, diff --git a/src/mainboard/google/octopus/variants/baseboard/devicetree.cb b/src/mainboard/google/octopus/variants/baseboard/devicetree.cb index 138499c..671150d 100644 --- a/src/mainboard/google/octopus/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/octopus/variants/baseboard/devicetree.cb @@ -55,7 +55,7 @@ register "lpss_s0ix_enable" = "true"
# Enable DPTF - register "dptf_enable" = "1" + register "dptf_enable" = "true"
# Enable Audio Clock and Power gating register "hdaudio_clk_gate_enable" = "1" diff --git a/src/mainboard/google/poppy/variants/atlas/devicetree.cb b/src/mainboard/google/poppy/variants/atlas/devicetree.cb index 04df902..a3bd3fa 100644 --- a/src/mainboard/google/poppy/variants/atlas/devicetree.cb +++ b/src/mainboard/google/poppy/variants/atlas/devicetree.cb @@ -28,7 +28,7 @@ register "gpe0_dw2" = "GPP_E"
# Enable DPTF - register "dptf_enable" = "1" + register "dptf_enable" = "true"
# Enable S0ix register "s0ix_enable" = true diff --git a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb index feea932..f47876a 100644 --- a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb @@ -19,7 +19,7 @@ register "gpe0_dw2" = "GPP_E"
# Enable DPTF - register "dptf_enable" = "1" + register "dptf_enable" = "true"
# Enable S0ix register "s0ix_enable" = true diff --git a/src/mainboard/google/poppy/variants/nami/devicetree.cb b/src/mainboard/google/poppy/variants/nami/devicetree.cb index 139a3c8..256a661 100644 --- a/src/mainboard/google/poppy/variants/nami/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nami/devicetree.cb @@ -28,7 +28,7 @@ register "gpe0_dw2" = "GPP_E"
# Enable DPTF - register "dptf_enable" = "1" + register "dptf_enable" = "true"
# Enable S0ix register "s0ix_enable" = true diff --git a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb index 363b614..3a04b51 100644 --- a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb @@ -28,7 +28,7 @@ register "gpe0_dw2" = "GPP_E"
# Enable DPTF - register "dptf_enable" = "1" + register "dptf_enable" = "true"
# Enable S0ix register "s0ix_enable" = true diff --git a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb index 97b0c20..7c92dee 100644 --- a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb @@ -21,7 +21,7 @@ register "gpe0_dw2" = "GPP_E"
# Enable DPTF - register "dptf_enable" = "1" + register "dptf_enable" = "true"
# Enable S0ix register "s0ix_enable" = true diff --git a/src/mainboard/google/poppy/variants/rammus/devicetree.cb b/src/mainboard/google/poppy/variants/rammus/devicetree.cb index 3743385..4345f73 100644 --- a/src/mainboard/google/poppy/variants/rammus/devicetree.cb +++ b/src/mainboard/google/poppy/variants/rammus/devicetree.cb @@ -28,7 +28,7 @@ register "gpe0_dw2" = "GPP_E"
# Enable DPTF - register "dptf_enable" = "1" + register "dptf_enable" = "true"
# Enable S0ix register "s0ix_enable" = true diff --git a/src/mainboard/google/poppy/variants/soraka/devicetree.cb b/src/mainboard/google/poppy/variants/soraka/devicetree.cb index 2d1a509..3d2767c 100644 --- a/src/mainboard/google/poppy/variants/soraka/devicetree.cb +++ b/src/mainboard/google/poppy/variants/soraka/devicetree.cb @@ -28,7 +28,7 @@ register "gpe0_dw2" = "GPP_E"
# Enable DPTF - register "dptf_enable" = "1" + register "dptf_enable" = "true"
# Enable S0ix register "s0ix_enable" = true diff --git a/src/mainboard/google/puff/variants/baseboard/devicetree.cb b/src/mainboard/google/puff/variants/baseboard/devicetree.cb index 08880cb..2eee315 100644 --- a/src/mainboard/google/puff/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/puff/variants/baseboard/devicetree.cb @@ -30,7 +30,7 @@ # Enable S0ix register "s0ix_enable" = "true" # Enable DPTF - register "dptf_enable" = "1" + register "dptf_enable" = "true" register "power_limits_config" = "{ .tdp_pl1_override = 15, .tdp_pl2_override = 64, diff --git a/src/mainboard/google/reef/variants/baseboard/devicetree.cb b/src/mainboard/google/reef/variants/baseboard/devicetree.cb index 1192a5f..1207bb3 100644 --- a/src/mainboard/google/reef/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/reef/variants/baseboard/devicetree.cb @@ -46,7 +46,7 @@ register "emmc_rx_cmd_data_cntl2" = "0x10008"
# Enable DPTF - register "dptf_enable" = "1" + register "dptf_enable" = "true"
# PL1 override 12 W: the energy calculation is wrong with the # current VR solution. Experiments show that SoC TDP max (6W) can diff --git a/src/mainboard/google/reef/variants/coral/devicetree.cb b/src/mainboard/google/reef/variants/coral/devicetree.cb index df39932..8ec7861 100644 --- a/src/mainboard/google/reef/variants/coral/devicetree.cb +++ b/src/mainboard/google/reef/variants/coral/devicetree.cb @@ -46,7 +46,7 @@ register "emmc_rx_cmd_data_cntl2" = "0x10008"
# Enable DPTF - register "dptf_enable" = "1" + register "dptf_enable" = "true"
# PL1 override 12 W: the energy calculation is wrong with the # current VR solution. Experiments show that SoC TDP max (6W) can diff --git a/src/mainboard/google/reef/variants/pyro/devicetree.cb b/src/mainboard/google/reef/variants/pyro/devicetree.cb index 022dc8b..cd257d0 100644 --- a/src/mainboard/google/reef/variants/pyro/devicetree.cb +++ b/src/mainboard/google/reef/variants/pyro/devicetree.cb @@ -46,7 +46,7 @@ register "emmc_rx_cmd_data_cntl2" = "0x10008"
# Enable DPTF - register "dptf_enable" = "1" + register "dptf_enable" = "true"
# PL1 override 12 W: the energy calculation is wrong with the # current VR solution. Experiments show that SoC TDP max (6W) can diff --git a/src/mainboard/google/reef/variants/sand/devicetree.cb b/src/mainboard/google/reef/variants/sand/devicetree.cb index f97614d..8002af0 100644 --- a/src/mainboard/google/reef/variants/sand/devicetree.cb +++ b/src/mainboard/google/reef/variants/sand/devicetree.cb @@ -43,7 +43,7 @@ register "emmc_rx_cmd_data_cntl2" = "0x10008"
# Enable DPTF - register "dptf_enable" = "1" + register "dptf_enable" = "true"
# PL1 override 12 W: the energy calculation is wrong with the # current VR solution. Experiments show that SoC TDP max (6W) can diff --git a/src/mainboard/google/reef/variants/snappy/devicetree.cb b/src/mainboard/google/reef/variants/snappy/devicetree.cb index fd30ce7..7a712f9 100644 --- a/src/mainboard/google/reef/variants/snappy/devicetree.cb +++ b/src/mainboard/google/reef/variants/snappy/devicetree.cb @@ -46,7 +46,7 @@ register "emmc_rx_cmd_data_cntl2" = "0x10008"
# Enable DPTF - register "dptf_enable" = "1" + register "dptf_enable" = "true"
# PL1 override 12 W: the energy calculation is wrong with the # current VR solution. Experiments show that SoC TDP max (6W) can diff --git a/src/mainboard/google/rex/variants/baseboard/ovis/devicetree.cb b/src/mainboard/google/rex/variants/baseboard/ovis/devicetree.cb index 2cfa075..6439c0e 100644 --- a/src/mainboard/google/rex/variants/baseboard/ovis/devicetree.cb +++ b/src/mainboard/google/rex/variants/baseboard/ovis/devicetree.cb @@ -43,7 +43,7 @@ register "pch_pm_energy_report_enable" = "1"
# DPTF enable - register "dptf_enable" = "1" + register "dptf_enable" = "true"
# Temporary setting TCC of 100C = Tj max (110) - TCC_Offset (10) register "tcc_offset" = "10" diff --git a/src/mainboard/google/rex/variants/baseboard/ovis/devicetree_pre_prod.cb b/src/mainboard/google/rex/variants/baseboard/ovis/devicetree_pre_prod.cb index 18c4192..ccc6995 100644 --- a/src/mainboard/google/rex/variants/baseboard/ovis/devicetree_pre_prod.cb +++ b/src/mainboard/google/rex/variants/baseboard/ovis/devicetree_pre_prod.cb @@ -43,7 +43,7 @@ register "pch_pm_energy_report_enable" = "1"
# DPTF enable - register "dptf_enable" = "1" + register "dptf_enable" = "true"
# Temporary setting TCC of 100C = Tj max (110) - TCC_Offset (10) register "tcc_offset" = "10" diff --git a/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb b/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb index 58c725e..2d9f342 100644 --- a/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb +++ b/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb @@ -43,7 +43,7 @@ register "pch_pm_energy_report_enable" = "1"
# DPTF enable - register "dptf_enable" = "1" + register "dptf_enable" = "true"
# Setting TCC of 100C = Tj max (110) - TCC_Offset (10) register "tcc_offset" = "10" diff --git a/src/mainboard/google/rex/variants/baseboard/rex/devicetree_pre_prod.cb b/src/mainboard/google/rex/variants/baseboard/rex/devicetree_pre_prod.cb index 9e8f870..741d8a4 100644 --- a/src/mainboard/google/rex/variants/baseboard/rex/devicetree_pre_prod.cb +++ b/src/mainboard/google/rex/variants/baseboard/rex/devicetree_pre_prod.cb @@ -43,7 +43,7 @@ register "pch_pm_energy_report_enable" = "1"
# DPTF enable - register "dptf_enable" = "1" + register "dptf_enable" = "true"
# Enable CNVi BT register "cnvi_bt_core" = "true" diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb index 7eec7a8..d245844 100644 --- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb +++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb @@ -28,7 +28,7 @@ register "PchUsb2PhySusPgDisable" = "1"
register "s0ix_enable" = "true" - register "dptf_enable" = "1" + register "dptf_enable" = "true" register "satapwroptimize" = "1" register "power_limits_config" = "{ .tdp_pl1_override = 25, diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb index d10fd1f..8fe366d 100644 --- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb +++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb @@ -31,7 +31,7 @@ register "PchUsb2PhySusPgDisable" = "1"
register "s0ix_enable" = "true" - register "dptf_enable" = "1" + register "dptf_enable" = "true" register "satapwroptimize" = "1" register "AcousticNoiseMitigation" = "1" register "SlowSlewRateForIa" = "2" diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index 4ff518e..2d2b431 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -198,7 +198,7 @@ register "s0ix_enable" = "true"
# Enable DPTF - register "dptf_enable" = "1" + register "dptf_enable" = "true"
# Enable External Bypass register "external_bypass" = "1" diff --git a/src/mainboard/intel/adlrvp/devicetree.cb b/src/mainboard/intel/adlrvp/devicetree.cb index a6bad13..1a2788e 100644 --- a/src/mainboard/intel/adlrvp/devicetree.cb +++ b/src/mainboard/intel/adlrvp/devicetree.cb @@ -133,7 +133,7 @@ register "tcss_aux_ori" = "0"
register "s0ix_enable" = "true" - register "dptf_enable" = "1" + register "dptf_enable" = "true"
register "serial_io_i2c_mode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, diff --git a/src/mainboard/intel/adlrvp/devicetree_n.cb b/src/mainboard/intel/adlrvp/devicetree_n.cb index c01613c..1ea7334 100644 --- a/src/mainboard/intel/adlrvp/devicetree_n.cb +++ b/src/mainboard/intel/adlrvp/devicetree_n.cb @@ -17,7 +17,7 @@ register "sagv" = "SaGv_Enabled"
# Enable DPTF - register "dptf_enable" = "1" + register "dptf_enable" = "true"
# eMMC HS400 register "emmc_enable_hs400_mode" = "1" diff --git a/src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb b/src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb index 7a46e10..dc0ae8a 100644 --- a/src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb +++ b/src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb @@ -49,7 +49,7 @@ register "emmc_tx_cmd_cntl" = "0x1305"
# Enable DPTF - register "dptf_enable" = "1" + register "dptf_enable" = "true"
# PL1 override: 7.5W setting gives a run-time 6W actual # Set RAPL PL2 to 15W. diff --git a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb index 1495366..e4e7baa 100644 --- a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb +++ b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb @@ -116,7 +116,7 @@ }"
# Enable DPTF - register "dptf_enable" = "1" + register "dptf_enable" = "true"
# Add PL1 and PL2 values register "power_limits_config[JSL_N4500_6W_CORE]" = "{ diff --git a/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb b/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb index be5ba44..6718d62 100644 --- a/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb +++ b/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb @@ -14,7 +14,7 @@ register "gpe0_dw2" = "GPP_E"
# Enable DPTF - register "dptf_enable" = "1" + register "dptf_enable" = "true"
# FSP Configuration register "IoBufferOwnership" = "0" diff --git a/src/mainboard/intel/kunimitsu/devicetree.cb b/src/mainboard/intel/kunimitsu/devicetree.cb index 458f559..5b809a6 100644 --- a/src/mainboard/intel/kunimitsu/devicetree.cb +++ b/src/mainboard/intel/kunimitsu/devicetree.cb @@ -14,7 +14,7 @@ register "gpe0_dw2" = "GPP_E"
# Enable DPTF - register "dptf_enable" = "1" + register "dptf_enable" = "true"
# FSP Configuration register "DspEnable" = "1" diff --git a/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb b/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb index e97d19e..23acba4 100644 --- a/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb +++ b/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb @@ -113,7 +113,7 @@ register "pch_hda_idisp_codec_enable" = "1"
# DPTF enable - register "dptf_enable" = "1" + register "dptf_enable" = "true"
device domain 0 on device ref igpu on end diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb index 69ec546..70adca6 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb @@ -71,7 +71,7 @@ register "s0ix_enable" = "true"
# Enable DPTF - register "dptf_enable" = "1" + register "dptf_enable" = "true"
# Add PL1 and PL2 values register "power_limits_config[POWER_LIMITS_U_2_CORE]" = "{ diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb index fbb8418..d1deea3 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb @@ -78,7 +78,7 @@ register "s0ix_enable" = "true"
# Enable DPTF - register "dptf_enable" = "1" + register "dptf_enable" = "true"
# Add PL1 and PL2 values register "power_limits_config[POWER_LIMITS_U_2_CORE]" = "{ diff --git a/src/mainboard/kontron/mal10/variants/mal10/devicetree.cb b/src/mainboard/kontron/mal10/variants/mal10/devicetree.cb index 953c819..3291e1d 100644 --- a/src/mainboard/kontron/mal10/variants/mal10/devicetree.cb +++ b/src/mainboard/kontron/mal10/variants/mal10/devicetree.cb @@ -3,7 +3,7 @@ chip soc/intel/apollolake
register "enable_vtd" = "1" - register "dptf_enable" = "1" + register "dptf_enable" = "true"
device domain 0 on device pci 00.0 on end # Host Bridge diff --git a/src/mainboard/libretrend/lt1000/devicetree.cb b/src/mainboard/libretrend/lt1000/devicetree.cb index 4f7d7eb..e3ef140 100644 --- a/src/mainboard/libretrend/lt1000/devicetree.cb +++ b/src/mainboard/libretrend/lt1000/devicetree.cb @@ -24,7 +24,7 @@ register "gpe0_dw2" = "GPP_E"
# Disable DPTF - register "dptf_enable" = "0" + register "dptf_enable" = "false"
# FSP Configuration register "DspEnable" = "1" diff --git a/src/mainboard/protectli/vault_kbl/devicetree.cb b/src/mainboard/protectli/vault_kbl/devicetree.cb index 9b0357f..fd931e7 100644 --- a/src/mainboard/protectli/vault_kbl/devicetree.cb +++ b/src/mainboard/protectli/vault_kbl/devicetree.cb @@ -15,7 +15,7 @@ register "eist_enable" = "true"
# Disable DPTF - register "dptf_enable" = "0" + register "dptf_enable" = "false"
register "tcc_offset" = "5" # TCC of 95C
diff --git a/src/mainboard/purism/librem_skl/devicetree.cb b/src/mainboard/purism/librem_skl/devicetree.cb index 5b448f9..257bb8a 100644 --- a/src/mainboard/purism/librem_skl/devicetree.cb +++ b/src/mainboard/purism/librem_skl/devicetree.cb @@ -35,7 +35,7 @@ register "gpe0_dw2" = "GPP_E"
# Disable DPTF - register "dptf_enable" = "0" + register "dptf_enable" = "false"
# FSP Configuration register "DspEnable" = "0" diff --git a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb index 311d96c..02b358a 100644 --- a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb +++ b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb @@ -16,7 +16,7 @@ register "gpe0_dw2" = "GPP_E"
# Disable DPTF - register "dptf_enable" = "0" + register "dptf_enable" = "false"
# FSP Configuration register "DspEnable" = "0" diff --git a/src/soc/intel/elkhartlake/chip.h b/src/soc/intel/elkhartlake/chip.h index e3a23b2..061621c 100644 --- a/src/soc/intel/elkhartlake/chip.h +++ b/src/soc/intel/elkhartlake/chip.h @@ -130,7 +130,7 @@ /* Enable S0iX support */ bool s0ix_enable; /* Enable DPTF support */ - int dptf_enable; + bool dptf_enable;
/* Deep SX enable for both AC and DC */ int deep_s3_enable_ac; diff --git a/src/soc/intel/pantherlake/chip.h b/src/soc/intel/pantherlake/chip.h index 3872916..79d7f26 100644 --- a/src/soc/intel/pantherlake/chip.h +++ b/src/soc/intel/pantherlake/chip.h @@ -88,7 +88,7 @@ /* Support for TBT PCIe root ports and DMA controllers with D3Hot->D3Cold */ uint8_t TcssD3ColdDisable; /* Enable DPTF support */ - int dptf_enable; + bool dptf_enable;
/* Deep SX enable for both AC and DC */ int deep_s3_enable_ac; diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h index 630317a..f0cecb3 100644 --- a/src/soc/intel/tigerlake/chip.h +++ b/src/soc/intel/tigerlake/chip.h @@ -149,7 +149,7 @@ uint8_t TcssD3HotDisable;
/* Enable DPTF support */ - int dptf_enable; + bool dptf_enable;
/* Deep SX enable for both AC and DC */ int deep_s3_enable_ac;
-
Elyes Haouas (Code Review)