Change in coreboot[master]: mainboard/nf81-t56n-lf: Add temperature sensor configuration

[Renze Nicolai (Code Review)]

Renze Nicolai has uploaded this change for review. ( https://review.coreboot.org/22966

Change subject: mainboard/nf81-t56n-lf: Add temperature sensor configuration
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mainboard/nf81-t56n-lf: Add temperature sensor configuration

This patch adds the temperature sensor type device tree setting,
configured to be the default value as stated in the superio datasheet.

(page 60)

bit 7-4: reserved (0)
bit 3: T3_MODE 1 (default) = BJT, 0 = thermistor
bit 2: T2_MODE 1 (default) = BJT, 0 = thermistor
bit 1: T1_MODE 1 (default) = BJT, 0 = thermistor
bit 0: reserved (0)

This results in a default value of 0x0E

This change is needed to make sure behaviour does not change after
applying change 22935 which adds the temperature sensor type
devicetree configuration option

Change-Id: I42980988267621def6576f771f1d8a853500e867
Signed-off-by: Renze Nicolai 
---
M src/mainboard/jetway/nf81-t56n-lf/devicetree.cb
1 file changed, 1 insertion(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/22966/1

diff --git a/src/mainboard/jetway/nf81-t56n-lf/devicetree.cb b/src/mainboard/jetway/nf81-t56n-lf/devicetree.cb
index 0db35ce..dd442b2 100644
--- a/src/mainboard/jetway/nf81-t56n-lf/devicetree.cb
+++ b/src/mainboard/jetway/nf81-t56n-lf/devicetree.cb
@@ -68,6 +68,7 @@
    							register "hwm_fan1_seg2_speed_count" = "0x0e"
    							register "hwm_fan1_seg3_speed_count" = "0x07"
    							register "hwm_fan1_temp_map_sel" = "0x8c"
+								register "hwm_temp_sensor_type" = "0x0E"	# default value
 #
 # XXX: 4e is the default index port and .xy is the
 # LDN indexing the pnp_info array found in the superio.c