[S] Change in coreboot[master]: soc/intel/meteorlake: Update pcie snoop/no-snoop latency

[Paul Menzel (Code Review)]

Attention is currently required from: Bora Guvendik, Tarun Tuli, Jérémy Compostella, Ravishankar Sarawadi, Kapil Porwal.

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68308 )

Change subject: soc/intel/meteorlake: Update pcie snoop/no-snoop latency
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Patch Set 6:

(5 comments)

Commit Message:

https://review.coreboot.org/c/coreboot/+/68308/comment/4d62cec7_fbb19be0 
PS6, Line 7: Update
Increase

https://review.coreboot.org/c/coreboot/+/68308/comment/025e2439_ea59efbb 
PS6, Line 10: This fixes an issue where pcie
            : was not power gating and blocked S0ix entry.
I prefer to start commit message with a problem description.

https://review.coreboot.org/c/coreboot/+/68308/comment/9ca39e5b_1f2187b3 
PS6, Line 12: 
Is this a work around? Is this a hardware problem? Are these values documented in some datasheet?

https://review.coreboot.org/c/coreboot/+/68308/comment/0c7666ce_6194d7dd 
PS6, Line 13: BUG=none
Why?

File src/soc/intel/meteorlake/pcie.c:

https://review.coreboot.org/c/coreboot/+/68308/comment/93712beb_985c87c1 
PS6, Line 9: 
Why do you put it here, and not `src/include/device/pciexp.h`?