Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38698 )
Change subject: vc/amd/fsp/picasso: Add PCIe and DDI helpers ......................................................................
vc/amd/fsp/picasso: Add PCIe and DDI helpers
Add a file for generating PCIe and DDI descriptors that will be understandable to the FSP.
Signed-off-by: Marshall Dawson marshalldawson3rd@gmail.com Change-Id: Iaa4d81a0f2909cb66e551e34e1f3fa4725560d60 --- A src/vendorcode/amd/fsp/picasso/platform_descriptors.h 1 file changed, 155 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/38698/1
diff --git a/src/vendorcode/amd/fsp/picasso/platform_descriptors.h b/src/vendorcode/amd/fsp/picasso/platform_descriptors.h new file mode 100644 index 0000000..71603d2 --- /dev/null +++ b/src/vendorcode/amd/fsp/picasso/platform_descriptors.h @@ -0,0 +1,155 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * These definitions are used to describe PCIe bifurcation and display physical + * connector types connected to the SOC. + */ + +#ifndef __PI_PICASSO_PLATFORM_DESCRIPTORS_H__ +#define __PI_PICASSO_PLATFORM_DESCRIPTORS_H__ + +/* Engine descriptor type */ +typedef enum { + UNUSED_ENGINE = 0, // Unused descriptor + PCIE_ENGINE = 1, // PCIe port + USB_ENGINE = 2, // USB port + SATA_ENGINE = 3, // SATA + DP_ENGINE = 8, // Digital Display + ETHERNET_ENGINE = 0x10, // Ethernet (GBe, XGBe) + MAX_ENGINE // Max engine type for boundary check. +} dxio_engine_type; + +/* PCIe link capability/speed */ +typedef enum { + GEN_MAX, // Maximum supported + GEN1 = 1, // Gen1 + GEN2, // Gen2 + GEN3, // Gen3 + GEN_INVALID // Max Gen for boundary check +} dxio_link_speed_cap; + +/* SATA ChannelType initialization */ +typedef enum { + SATA_CHANNEL_OTHER, // Default Channel Type + SATA_CHANNEL_SHORT, // Short Trace Channel Type + SATA_CHANNEL_LONG // Long Trace Channel Type +} dxio_sata_channel_type; + +/* CLKREQ for PCIe type descriptors */ +typedef enum { + CLK_DISABLE = 0x00, + CLK_REQ0, + CLK_REQ1, + CLK_REQ2, + CLK_REQ3, + CLK_REQ4, + CLK_REQ5, + CLK_REQ6, + CLK_REQ7, + CLK_REQ8, + CLK_REQGFX = 0x0c, +} cpm_clk_req; + +/* PCIe link ASPM initialization */ +typedef enum { + ASPM_DISABLED, // Disabled + ASPM_L0s, // PCIe L0s link state + ASPM_L1, // PCIe L1 link state + ASPM_L0sL1, // PCIe L0s & L1 link state + ASPM_MAX // Not valid value, used to verify input +} dxio_aspm_type; + +/* DDI Aux channel */ +typedef enum { + AUX1, // Aux1 + AUX2, // Aux2 + AUX3, // Aux3 + AUX4, // Aux4 + AUX5, // Aux5 + AUX6, // Aux6 + AUX_MAX // Not valid value, used to verify input +} pcie_aux_type; + +/* DDI Hdp Index */ +typedef enum { + HDP1, // Hdp1 + HDP2, // Hdp2 + HDP3, // Hdp3 + HDP4, // Hdp4 + HDP5, // Hdp5 + HDP6, // Hdp6 + HDP_MAX // Not valid value, used to verify input +} pcie_hdp_type; + +/* DDI display connector type */ +typedef enum { + DP, // DP + EDP, // eDP + SINGLE_LINK_DVI, // Single Link DVI-D + DUAL_LINK_DVI, // Dual Link DVI-D + HDMI, // HDMI + DP_TO_VGA, // DP-to-VGA + DP_TO_LVDS, // DP-to-LVDS + NUTMEG_DP_TO_VGA, // Hudson-2 NutMeg DP-to-VGA + SINGLE_LINK_DVI_I, // Single Link DVI-I + CRT, // CRT (VGA) + LVDS, // LVDS + EDP_TO_LVDS, // eDP-to-LVDS translator chip without AMD SW init + EDP_TO_LVDS_SW, // eDP-to-LVDS translator which requires AMD SW init + AUTO_DETECT, // VBIOS auto detect connector type + UNUSED_PTYPE, // UnusedType + MAX_CONNECTOR_TYPE // Not valid value, used to verify input +} pcie_connector_type; + +/* DDI Descriptor: used for configuring display outputs */ +typedef struct __packed { + uint8_t connector_type; + uint8_t aux_index; + uint8_t hdp_index; + uint8_t reserved; +} fsp_ddi_descriptor; + +/* PCIe Descriptor: used for assigning lanes, bifurcation and other settings */ +typedef struct __packed { + uint8_t engine_type; + uint8_t start_lane; // Start lane of the pci device + uint8_t end_lane; // End lane of the pci device + uint8_t gpio_group_id; // FCH reset number. 0 is global reset + unsigned int port_present:1; // Should be TRUE if train link + unsigned int reserved_3:7; + unsigned int device_number:5; // Desired root port device number + unsigned int function_number:3; // Desired root port function number + unsigned int link_speed_capability:2; + unsigned int auto_spd_change:2; + unsigned int eq_preset:4; + unsigned int link_aspm:2; + unsigned int link_aspm_L1_1:1; + unsigned int link_aspm_L1_2:1; + unsigned int clk_req:4; + uint8_t link_hotplug; + uint8_t slot_power_limit; + unsigned int slot_power_limit_scale:2; + unsigned int reserved_4:6; + unsigned int link_compliance_mode:1; + unsigned int link_safe_mode:1; + unsigned int sb_link:1; + unsigned int clk_pm_support:1; + unsigned int channel_type:3; + unsigned int turn_off_unused_lanes:1; + uint8_t reserved[4]; +} fsp_pcie_descriptor; + +#endif /* __PI_PICASSO_PLATFORM_DESCRIPTORS_H__ */
Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38698 )
Change subject: vc/amd/fsp/picasso: Add PCIe and DDI helpers ......................................................................
Patch Set 1:
(7 comments)
https://review.coreboot.org/c/coreboot/+/38698/1/src/vendorcode/amd/fsp/pica... File src/vendorcode/amd/fsp/picasso/platform_descriptors.h:
https://review.coreboot.org/c/coreboot/+/38698/1/src/vendorcode/amd/fsp/pica... PS1, Line 37: GEN_MAX, // Maximum supported I'd add a = 0 here to make t clearer that the absolute values matter here and not only the symbolic names. the resulting values stay the same
https://review.coreboot.org/c/coreboot/+/38698/1/src/vendorcode/amd/fsp/pica... PS1, Line 46: SATA_CHANNEL_OTHER, // Default Channel Type same here
https://review.coreboot.org/c/coreboot/+/38698/1/src/vendorcode/amd/fsp/pica... PS1, Line 68: ASPM_DISABLED, // Disabled same here
https://review.coreboot.org/c/coreboot/+/38698/1/src/vendorcode/amd/fsp/pica... PS1, Line 77: AUX1, // Aux1 same here
https://review.coreboot.org/c/coreboot/+/38698/1/src/vendorcode/amd/fsp/pica... PS1, Line 88: HDP1, // Hdp1 same here
https://review.coreboot.org/c/coreboot/+/38698/1/src/vendorcode/amd/fsp/pica... PS1, Line 99: DP, // DP same here
https://review.coreboot.org/c/coreboot/+/38698/1/src/vendorcode/amd/fsp/pica... PS1, Line 131: unsigned int i'd strongly prefer uint32_t here, since it makes the sizes more obvious. same below
Marshall Dawson has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38698 )
Change subject: vc/amd/fsp/picasso: Add PCIe and DDI helpers ......................................................................
Patch Set 1:
(2 comments)
https://review.coreboot.org/c/coreboot/+/38698/1/src/vendorcode/amd/fsp/pica... File src/vendorcode/amd/fsp/picasso/platform_descriptors.h:
https://review.coreboot.org/c/coreboot/+/38698/1/src/vendorcode/amd/fsp/pica... PS1, Line 37: GEN_MAX, // Maximum supported
I'd add a = 0 here to make t clearer that the absolute values matter here and not only the symbolic […]
It sometimes seems to depend on who's reviewing. I believe I've seen that requested to be omitted. OTOH, maybe there's a better case for clarity here since the info is shared between coreboot and FSP.
Hmm, the values mixed hex and decimal numbers above. I don't recall now if this was originally copy/pasted out of AGESA.
https://review.coreboot.org/c/coreboot/+/38698/1/src/vendorcode/amd/fsp/pica... PS1, Line 131: unsigned int
i'd strongly prefer uint32_t here, since it makes the sizes more obvious. […]
Ew, yeah I agree.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38698 )
Change subject: vc/amd/fsp/picasso: Add PCIe and DDI helpers ......................................................................
Patch Set 1: Code-Review+1
(1 comment)
https://review.coreboot.org/c/coreboot/+/38698/1/src/vendorcode/amd/fsp/pica... File src/vendorcode/amd/fsp/picasso/platform_descriptors.h:
https://review.coreboot.org/c/coreboot/+/38698/1/src/vendorcode/amd/fsp/pica... PS1, Line 37: GEN_MAX, // Maximum supported
It sometimes seems to depend on who's reviewing. I believe I've seen that requested to be omitted. […]
I would prefer a `GEN_MAX = 0` over the current `GEN1 = 1`
Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38698 )
Change subject: vc/amd/fsp/picasso: Add PCIe and DDI helpers ......................................................................
Patch Set 1:
(1 comment)
do you want to update the patch or should i take over from here?
https://review.coreboot.org/c/coreboot/+/38698/1/src/vendorcode/amd/fsp/pica... File src/vendorcode/amd/fsp/picasso/platform_descriptors.h:
https://review.coreboot.org/c/coreboot/+/38698/1/src/vendorcode/amd/fsp/pica... PS1, Line 37: GEN_MAX, // Maximum supported
It sometimes seems to depend on who's reviewing. I believe I've seen that requested to be omitted. OTOH, maybe there's a better case for clarity here since the info is shared between coreboot and FSP.
When I see enums without at least one explicit value assignemnt, I'd assume that only the symbolic names and not the underlying raw values are used/matter. But yeah, different reviewers might have different opinions on things.
Hmm, the values mixed hex and decimal numbers above. I don't recall now if this was originally copy/pasted out of AGESA.
Oh, missed that one; just making all values hex values might be a good idea. Also aligning the = signs with tabs slightly improves readability; especially since the comments are already tab-aligned
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38698 )
Change subject: vc/amd/fsp/picasso: Add PCIe and DDI helpers ......................................................................
Patch Set 1:
(2 comments)
https://review.coreboot.org/c/coreboot/+/38698/1/src/vendorcode/amd/fsp/pica... File src/vendorcode/amd/fsp/picasso/platform_descriptors.h:
https://review.coreboot.org/c/coreboot/+/38698/1/src/vendorcode/amd/fsp/pica... PS1, Line 4: 2015 Is that correct? Maybe use SPDX headers right away.
https://review.coreboot.org/c/coreboot/+/38698/1/src/vendorcode/amd/fsp/pica... PS1, Line 77: AUX1, // Aux1 Are these comments needed?
Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38698 )
Change subject: vc/amd/fsp/picasso: Add PCIe and DDI helpers ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38698/1/src/vendorcode/amd/fsp/pica... File src/vendorcode/amd/fsp/picasso/platform_descriptors.h:
https://review.coreboot.org/c/coreboot/+/38698/1/src/vendorcode/amd/fsp/pica... PS1, Line 131: unsigned int
Ew, yeah I agree.
i think unsigend int was used here, since this are bitfields and not full uint32_t.
sadly the memory layout of bitfield strucs is undefined behavior in c; since this will always be compiled for a little endian architecture, this should still work in practice. the compiler can basically choose if it fills the bitfields in the dwords from top or bottom
Felix Held has uploaded a new patch set (#2) to the change originally created by Marshall Dawson. ( https://review.coreboot.org/c/coreboot/+/38698 )
Change subject: vc/amd/fsp/picasso: Add PCIe and DDI helpers ......................................................................
vc/amd/fsp/picasso: Add PCIe and DDI helpers
Add a file for generating PCIe and DDI descriptors that will be understandable to the FSP.
Signed-off-by: Marshall Dawson marshalldawson3rd@gmail.com Signed-off-by: Felix Held felix-coreboot@felixheld.de Change-Id: Iaa4d81a0f2909cb66e551e34e1f3fa4725560d60 --- A src/vendorcode/amd/fsp/picasso/platform_descriptors.h 1 file changed, 145 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/38698/2
Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38698 )
Change subject: vc/amd/fsp/picasso: Add PCIe and DDI helpers ......................................................................
Patch Set 2:
(9 comments)
https://review.coreboot.org/c/coreboot/+/38698/1/src/vendorcode/amd/fsp/pica... File src/vendorcode/amd/fsp/picasso/platform_descriptors.h:
https://review.coreboot.org/c/coreboot/+/38698/1/src/vendorcode/amd/fsp/pica... PS1, Line 4: 2015
Is that correct? Maybe use SPDX headers right away.
Done
https://review.coreboot.org/c/coreboot/+/38698/1/src/vendorcode/amd/fsp/pica... PS1, Line 37: GEN_MAX, // Maximum supported
It sometimes seems to depend on who's reviewing. […]
Done
https://review.coreboot.org/c/coreboot/+/38698/1/src/vendorcode/amd/fsp/pica... PS1, Line 46: SATA_CHANNEL_OTHER, // Default Channel Type
same here
Done
https://review.coreboot.org/c/coreboot/+/38698/1/src/vendorcode/amd/fsp/pica... PS1, Line 68: ASPM_DISABLED, // Disabled
same here
Done
https://review.coreboot.org/c/coreboot/+/38698/1/src/vendorcode/amd/fsp/pica... PS1, Line 77: AUX1, // Aux1
Are these comments needed?
Done
https://review.coreboot.org/c/coreboot/+/38698/1/src/vendorcode/amd/fsp/pica... PS1, Line 77: AUX1, // Aux1
same here
Done
https://review.coreboot.org/c/coreboot/+/38698/1/src/vendorcode/amd/fsp/pica... PS1, Line 88: HDP1, // Hdp1
same here
Done
https://review.coreboot.org/c/coreboot/+/38698/1/src/vendorcode/amd/fsp/pica... PS1, Line 99: DP, // DP
same here
Done
https://review.coreboot.org/c/coreboot/+/38698/1/src/vendorcode/amd/fsp/pica... PS1, Line 131: unsigned int
i think unsigend int was used here, since this are bitfields and not full uint32_t. […]
added a comment about this. there is probably no better option to do this in c that is similarly convenient to use and this code will never be built for big endian machines
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38698 )
Change subject: vc/amd/fsp/picasso: Add PCIe and DDI helpers ......................................................................
Patch Set 2: Code-Review+1
Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38698 )
Change subject: vc/amd/fsp/picasso: Add PCIe and DDI helpers ......................................................................
Patch Set 2: Code-Review+2
Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/38698 )
Change subject: vc/amd/fsp/picasso: Add PCIe and DDI helpers ......................................................................
vc/amd/fsp/picasso: Add PCIe and DDI helpers
Add a file for generating PCIe and DDI descriptors that will be understandable to the FSP.
Signed-off-by: Marshall Dawson marshalldawson3rd@gmail.com Signed-off-by: Felix Held felix-coreboot@felixheld.de Change-Id: Iaa4d81a0f2909cb66e551e34e1f3fa4725560d60 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38698 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Paul Menzel paulepanter@users.sourceforge.net Reviewed-by: Raul Rangel rrangel@chromium.org --- A src/vendorcode/amd/fsp/picasso/platform_descriptors.h 1 file changed, 145 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Raul Rangel: Looks good to me, approved
diff --git a/src/vendorcode/amd/fsp/picasso/platform_descriptors.h b/src/vendorcode/amd/fsp/picasso/platform_descriptors.h new file mode 100644 index 0000000..58ed4a9 --- /dev/null +++ b/src/vendorcode/amd/fsp/picasso/platform_descriptors.h @@ -0,0 +1,145 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +/* + * These definitions are used to describe PCIe bifurcation and display physical + * connector types connected to the SOC. + */ + +#ifndef __PI_PICASSO_PLATFORM_DESCRIPTORS_H__ +#define __PI_PICASSO_PLATFORM_DESCRIPTORS_H__ + +/* Engine descriptor type */ +typedef enum { + UNUSED_ENGINE = 0x00, // Unused descriptor + PCIE_ENGINE = 0x01, // PCIe port + USB_ENGINE = 0x02, // USB port + SATA_ENGINE = 0x03, // SATA + DP_ENGINE = 0x08, // Digital Display + ETHERNET_ENGINE = 0x10, // Ethernet (GBe, XGBe) + MAX_ENGINE // Max engine type for boundary check. +} dxio_engine_type; + +/* PCIe link capability/speed */ +typedef enum { + GEN_MAX = 0, // Maximum supported + GEN1, + GEN2, + GEN3, + GEN_INVALID // Max Gen for boundary check +} dxio_link_speed_cap; + +/* SATA ChannelType initialization */ +typedef enum { + SATA_CHANNEL_OTHER = 0, // Default Channel Type + SATA_CHANNEL_SHORT, // Short Trace Channel Type + SATA_CHANNEL_LONG // Long Trace Channel Type +} dxio_sata_channel_type; + +/* CLKREQ for PCIe type descriptors */ +typedef enum { + CLK_DISABLE = 0x00, + CLK_REQ0, + CLK_REQ1, + CLK_REQ2, + CLK_REQ3, + CLK_REQ4, + CLK_REQ5, + CLK_REQ6, + CLK_REQ7, + CLK_REQ8, + CLK_REQGFX = 0x0c, +} cpm_clk_req; + +/* PCIe link ASPM initialization */ +typedef enum { + ASPM_DISABLED = 0, // Disabled + ASPM_L0s, // PCIe L0s link state + ASPM_L1, // PCIe L1 link state + ASPM_L0sL1, // PCIe L0s & L1 link state + ASPM_MAX // Not valid value, used to verify input +} dxio_aspm_type; + +/* DDI Aux channel */ +typedef enum { + AUX1 = 0, + AUX2, + AUX3, + AUX4, + AUX5, + AUX6, + AUX_MAX // Not valid value, used to verify input +} pcie_aux_type; + +/* DDI Hdp Index */ +typedef enum { + HDP1 = 0, + HDP2, + HDP3, + HDP4, + HDP5, + HDP6, + HDP_MAX // Not valid value, used to verify input +} pcie_hdp_type; + +/* DDI display connector type */ +typedef enum { + DP = 0, // DP + EDP, // eDP + SINGLE_LINK_DVI, // Single Link DVI-D + DUAL_LINK_DVI, // Dual Link DVI-D + HDMI, // HDMI + DP_TO_VGA, // DP-to-VGA + DP_TO_LVDS, // DP-to-LVDS + NUTMEG_DP_TO_VGA, // Hudson-2 NutMeg DP-to-VGA + SINGLE_LINK_DVI_I, // Single Link DVI-I + CRT, // CRT (VGA) + LVDS, // LVDS + EDP_TO_LVDS, // eDP-to-LVDS translator chip without AMD SW init + EDP_TO_LVDS_SW, // eDP-to-LVDS translator which requires AMD SW init + AUTO_DETECT, // VBIOS auto detect connector type + UNUSED_PTYPE, // UnusedType + MAX_CONNECTOR_TYPE // Not valid value, used to verify input +} pcie_connector_type; + +/* DDI Descriptor: used for configuring display outputs */ +typedef struct __packed { + uint8_t connector_type; + uint8_t aux_index; + uint8_t hdp_index; + uint8_t reserved; +} fsp_ddi_descriptor; + +/* PCIe Descriptor: used for assigning lanes, bifurcation and other settings */ +/* Since the code will always be compiled as little endian, using a bitfield struct should be + safe here. */ +typedef struct __packed { + uint8_t engine_type; + uint8_t start_lane; // Start lane of the pci device + uint8_t end_lane; // End lane of the pci device + uint8_t gpio_group_id; // FCH reset number. 0 is global reset + unsigned int port_present :1; // Should be TRUE if train link + unsigned int reserved_3 :7; + unsigned int device_number :5; // Desired root port device number + unsigned int function_number :3; // Desired root port function number + unsigned int link_speed_capability :2; + unsigned int auto_spd_change :2; + unsigned int eq_preset :4; + unsigned int link_aspm :2; + unsigned int link_aspm_L1_1 :1; + unsigned int link_aspm_L1_2 :1; + unsigned int clk_req :4; + uint8_t link_hotplug; + uint8_t slot_power_limit; + unsigned int slot_power_limit_scale :2; + unsigned int reserved_4 :6; + unsigned int link_compliance_mode :1; + unsigned int link_safe_mode :1; + unsigned int sb_link :1; + unsigned int clk_pm_support :1; + unsigned int channel_type :3; + unsigned int turn_off_unused_lanes :1; + uint8_t reserved[4]; +} fsp_pcie_descriptor; + +#endif /* __PI_PICASSO_PLATFORM_DESCRIPTORS_H__ */
9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38698 )
Change subject: vc/amd/fsp/picasso: Add PCIe and DDI helpers ......................................................................
Patch Set 3:
Automatic boot test returned (PASS/FAIL/TOTAL): 7/0/7 Emulation targets: EMULATION_QEMU_X86_Q35 using payload TianoCore : SUCCESS : https://lava.9esec.io/r/1848 EMULATION_QEMU_X86_Q35 using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/1847 EMULATION_QEMU_X86_I440FX using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/1846 Non-emulation targets: HP_Z220_SFF_WORKSTATION using payload TianoCore : SUCCESS : https://lava.9esec.io/r/1852 HP_Z220_SFF_WORKSTATION using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/1851 HP_COMPAQ_8200_ELITE_SFF_PC using payload TianoCore : SUCCESS : https://lava.9esec.io/r/1850 HP_COMPAQ_8200_ELITE_SFF_PC using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/1849
Please note: This test is under development and might not be accurate at all!
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9elements QA (Code Review) -
Angel Pons (Code Review)
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Felix Held (Code Review)
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Marshall Dawson (Code Review)
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Paul Menzel (Code Review)
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Raul Rangel (Code Review)