[S] Change in coreboot[master]: src/soc/nvidia: Remove unnecessary space after casts

[Elyes Haouas (Code Review)]

Attention is currently required from: Julius Werner.

Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69810 )

Change subject: src/soc/nvidia: Remove unnecessary space after casts
......................................................................

src/soc/nvidia: Remove unnecessary space after casts

Change-Id: I096e88158027ac22cf93a9450c869807dbc14670
Signed-off-by: Elyes Haouas 
---
M src/soc/nvidia/tegra124/dp.c
M src/soc/nvidia/tegra124/sor.c
M src/soc/nvidia/tegra210/dp.c
M src/soc/nvidia/tegra210/sor.c
M src/soc/nvidia/tegra210/spi.c
5 files changed, 19 insertions(+), 9 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/69810/1

diff --git a/src/soc/nvidia/tegra124/dp.c b/src/soc/nvidia/tegra124/dp.c
index 5da2c06..de98d65 100644
--- a/src/soc/nvidia/tegra124/dp.c
+++ b/src/soc/nvidia/tegra124/dp.c
@@ -28,7 +28,7 @@

static inline u32 tegra_dpaux_readl(struct tegra_dc_dp_data *dp, u32 reg)
 {
-	void *addr = dp->aux_base + (u32) (reg << 2);
+	void *addr = dp->aux_base + (u32)(reg << 2);
    u32 reg_val = READL(addr);
    return reg_val;
 }
@@ -36,7 +36,7 @@
 static inline void tegra_dpaux_writel(struct tegra_dc_dp_data *dp,
    				  u32 reg, u32 val)
 {
-	void *addr = dp->aux_base + (u32) (reg << 2);
+	void *addr = dp->aux_base + (u32)(reg << 2);
    WRITEL(val, addr);
 }

diff --git a/src/soc/nvidia/tegra124/sor.c b/src/soc/nvidia/tegra124/sor.c
index 3d2750f..8246a09 100644
--- a/src/soc/nvidia/tegra124/sor.c
+++ b/src/soc/nvidia/tegra124/sor.c
@@ -42,7 +42,7 @@

static inline u32 tegra_sor_readl(struct tegra_dc_sor_data *sor, u32 reg)
 {
-	void *addr = sor->base + (u32) (reg << 2);
+	void *addr = sor->base + (u32)(reg << 2);
    u32 reg_val = READL(addr);
    return reg_val;
 }
@@ -50,7 +50,7 @@
 static inline void tegra_sor_writel(struct tegra_dc_sor_data *sor,
    u32 reg, u32 val)
 {
-	void *addr = sor->base + (u32) (reg << 2);
+	void *addr = sor->base + (u32)(reg << 2);
    WRITEL(val, addr);
 }

diff --git a/src/soc/nvidia/tegra210/dp.c b/src/soc/nvidia/tegra210/dp.c
index f3bc208..f6f955c 100644
--- a/src/soc/nvidia/tegra210/dp.c
+++ b/src/soc/nvidia/tegra210/dp.c
@@ -36,7 +36,7 @@

static inline u32 tegra_dpaux_readl(struct tegra_dc_dp_data *dp, u32 reg)
 {
-	void *addr = dp->aux_base + (u32) (reg << 2);
+	void *addr = dp->aux_base + (u32)(reg << 2);
    u32 reg_val = READL(addr);
    return reg_val;
 }
@@ -44,7 +44,7 @@
 static inline void tegra_dpaux_writel(struct tegra_dc_dp_data *dp,
    				  u32 reg, u32 val)
 {
-	void *addr = dp->aux_base + (u32) (reg << 2);
+	void *addr = dp->aux_base + (u32)(reg << 2);
    WRITEL(val, addr);
 }

diff --git a/src/soc/nvidia/tegra210/sor.c b/src/soc/nvidia/tegra210/sor.c
index 91ea5f4..c24e0d6 100644
--- a/src/soc/nvidia/tegra210/sor.c
+++ b/src/soc/nvidia/tegra210/sor.c
@@ -44,7 +44,7 @@

static inline u32 tegra_sor_readl(struct tegra_dc_sor_data *sor, u32 reg)
 {
-	void *addr = sor->base + (u32) (reg << 2);
+	void *addr = sor->base + (u32)(reg << 2);
    u32 reg_val = READL(addr);
    return reg_val;
 }
@@ -52,7 +52,7 @@
 static inline void tegra_sor_writel(struct tegra_dc_sor_data *sor,
    u32 reg, u32 val)
 {
-	void *addr = sor->base + (u32) (reg << 2);
+	void *addr = sor->base + (u32)(reg << 2);
    WRITEL(val, addr);
 }

diff --git a/src/soc/nvidia/tegra210/spi.c b/src/soc/nvidia/tegra210/spi.c
index f8db110..b7bc685 100644
--- a/src/soc/nvidia/tegra210/spi.c
+++ b/src/soc/nvidia/tegra210/spi.c
@@ -478,7 +478,7 @@
    	dcache_clean_by_mva(spi->out_buf, bytes);

write32(&spi->dma_out->regs->apb_ptr,
-			(uintptr_t) & spi->regs->tx_fifo);
+			(uintptr_t)& spi->regs->tx_fifo);
    	write32(&spi->dma_out->regs->ahb_ptr, (uintptr_t)spi->out_buf);
    	setbits32(&spi->dma_out->regs->csr, APB_CSR_DIR);
    	setup_dma_params(spi, spi->dma_out);