Keith Hui has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38367 )
Change subject: sb/intel/i82371eb: Add PIIX4 definitions ......................................................................
sb/intel/i82371eb: Add PIIX4 definitions
These new definitions will be used by two other changes.
Change-Id: I242244c444f36af188c871dce037a7a9250206cd Signed-off-by: Keith Hui buurin@gmail.com --- M src/southbridge/intel/i82371eb/i82371eb.h 1 file changed, 5 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/38367/1
diff --git a/src/southbridge/intel/i82371eb/i82371eb.h b/src/southbridge/intel/i82371eb/i82371eb.h index 55242ef..bc5cfdb 100644 --- a/src/southbridge/intel/i82371eb/i82371eb.h +++ b/src/southbridge/intel/i82371eb/i82371eb.h @@ -40,6 +40,11 @@
#define XBCS 0x4e /* X-Bus chip select register */ #define GENCFG 0xb0 /* General configuration register */ +#define GPO2223 (1<<28) /* GPO22/23 */ +#define RTCCFG 0xcb /* Real time clock configuration register */ +#define RTC_POS_DECODE (1<<5) +#define UPPER_RAM_EN (1<<2) +#define RTC_ENABLE (1<<0)
/* IDE */ #define IDETIM_PRI 0x40 /* IDE timing register, primary channel */
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38367 )
Change subject: sb/intel/i82371eb: Add PIIX4 definitions ......................................................................
Patch Set 1: Code-Review+2
(1 comment)
https://review.coreboot.org/c/coreboot/+/38367/1/src/southbridge/intel/i8237... File src/southbridge/intel/i82371eb/i82371eb.h:
https://review.coreboot.org/c/coreboot/+/38367/1/src/southbridge/intel/i8237... PS1, Line 43: (1<<28) These should use spaces:
(1 << 28)
However, the rest of this file seems to be using this format, so it would be better to change that on a separate patch.
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38367 )
Change subject: sb/intel/i82371eb: Add PIIX4 definitions ......................................................................
Patch Set 2: Code-Review+1
Normally spaces are required around operators, but let’s be consistent here.
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/38367 )
Change subject: sb/intel/i82371eb: Add PIIX4 definitions ......................................................................
sb/intel/i82371eb: Add PIIX4 definitions
These new definitions will be used by two other changes.
Change-Id: I242244c444f36af188c871dce037a7a9250206cd Signed-off-by: Keith Hui buurin@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/38367 Reviewed-by: Paul Menzel paulepanter@users.sourceforge.net Reviewed-by: Angel Pons th3fanbus@gmail.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/southbridge/intel/i82371eb/i82371eb.h 1 file changed, 5 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Angel Pons: Looks good to me, approved
diff --git a/src/southbridge/intel/i82371eb/i82371eb.h b/src/southbridge/intel/i82371eb/i82371eb.h index 2b53010..a566af7 100644 --- a/src/southbridge/intel/i82371eb/i82371eb.h +++ b/src/southbridge/intel/i82371eb/i82371eb.h @@ -40,6 +40,11 @@
#define XBCS 0x4e /* X-Bus chip select register */ #define GENCFG 0xb0 /* General configuration register */ +#define GPO2223 (1<<28) /* GPO22/23 */ +#define RTCCFG 0xcb /* Real time clock configuration register */ +#define RTC_POS_DECODE (1<<5) +#define UPPER_RAM_EN (1<<2) +#define RTC_ENABLE (1<<0)
/* IDE */ #define IDETIM_PRI 0x40 /* IDE timing register, primary channel */
Keith Hui has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38367 )
Change subject: sb/intel/i82371eb: Add PIIX4 definitions ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38367/1/src/southbridge/intel/i8237... File src/southbridge/intel/i82371eb/i82371eb.h:
https://review.coreboot.org/c/coreboot/+/38367/1/src/southbridge/intel/i8237... PS1, Line 43: (1<<28)
These should use spaces: […]
Ack
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Angel Pons (Code Review) -
Keith Hui (Code Review)
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Patrick Georgi (Code Review)
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Paul Menzel (Code Review)