[S] Change in coreboot[main]: vc/amd/opensil/genoa_poc: remove xSIM-api dependency from opensil.h

[Felix Held (Code Review)]

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/80287?usp=email )

Change subject: vc/amd/opensil/genoa_poc: remove xSIM-api dependency from opensil.h
......................................................................

vc/amd/opensil/genoa_poc: remove xSIM-api dependency from opensil.h

Provide 3 separate functions for each openSIL time point instead of one,
so that we don't need the xSIM-api header file to be included in
opensil.h to decouple the coreboot code more form the openSIL code. This
will allow to create an openSIL stub implementation to already get most
of the coreboot-side SoC code in place before the openSIL source code is
done and released.

Signed-off-by: Felix Held 
Change-Id: I969bc0862560b7254c48f04e9a03387417f328bc
---
M src/soc/amd/genoa_poc/chip.c
M src/vendorcode/amd/opensil/genoa_poc/opensil.h
M src/vendorcode/amd/opensil/genoa_poc/ramstage.c
3 files changed, 20 insertions(+), 4 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/80287/1

diff --git a/src/soc/amd/genoa_poc/chip.c b/src/soc/amd/genoa_poc/chip.c
index d397800..13ede84 100644
--- a/src/soc/amd/genoa_poc/chip.c
+++ b/src/soc/amd/genoa_poc/chip.c
@@ -11,7 +11,7 @@
    default_dev_ops_root.write_acpi_tables = soc_acpi_write_tables;

setup_opensil();
-	opensil_entry(SIL_TP1);
+	opensil_xSIM_timepoint_1();

fch_init(chip_info);
 }
diff --git a/src/vendorcode/amd/opensil/genoa_poc/opensil.h b/src/vendorcode/amd/opensil/genoa_poc/opensil.h
index e225522..334903f 100644
--- a/src/vendorcode/amd/opensil/genoa_poc/opensil.h
+++ b/src/vendorcode/amd/opensil/genoa_poc/opensil.h
@@ -4,7 +4,6 @@
 #define _OPENSIL_H_

#include <acpi/acpi.h>
-#include <xSIM-api.h>

void SIL_STATUS_report(const char *function, const int status);
 // Add the memory map to dev, starting at index idx, returns last use idx
@@ -15,6 +14,8 @@
 void configure_mpio(void);

void setup_opensil(void);
-void opensil_entry(SIL_TIMEPOINT timepoint);
+void opensil_xSIM_timepoint_1(void);
+void opensil_xSIM_timepoint_2(void);
+void opensil_xSIM_timepoint_3(void);

#endif
diff --git a/src/vendorcode/amd/opensil/genoa_poc/ramstage.c b/src/vendorcode/amd/opensil/genoa_poc/ramstage.c
index 11289bb..758b284 100644
--- a/src/vendorcode/amd/opensil/genoa_poc/ramstage.c
+++ b/src/vendorcode/amd/opensil/genoa_poc/ramstage.c
@@ -129,7 +129,7 @@
    configure_mpio();
 }

-void opensil_entry(SIL_TIMEPOINT timepoint)
+static void opensil_entry(SIL_TIMEPOINT timepoint)
 {
    SIL_STATUS ret;
    SIL_TIMEPOINT tp = (uintptr_t)timepoint;
@@ -160,4 +160,19 @@
    }
 }

+void opensil_xSIM_timepoint_1(void)
+{
+	opensil_entry(SIL_TP1);
+}
+
+void opensil_xSIM_timepoint_2(void)
+{
+	opensil_entry(SIL_TP2);
+}
+
+void opensil_xSIM_timepoint_3(void)
+{
+	opensil_entry(SIL_TP3);
+}
+
 /* TODO: also call timepoints 2 and 3 from coreboot. Are they NOOP? */