Change in coreboot[master]: soc/intel/common/block/acpi: Factor out common pcie_rp_xx_xx.asl
Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46004 )
Change subject: soc/intel/common/block/acpi: Factor out common pcie_rp_xx_xx.asl ......................................................................
soc/intel/common/block/acpi: Factor out common pcie_rp_xx_xx.asl
This patch moves common PCIE RP ASL devices into common block acpi directory as part of pcie_rp_xx_xx to avoid duplicating the same ASL code block across SoC directory.
For PCH-LP pcie_rp_1_8.asl => To hold RP01-RP08 entries refer as 0:0x1C.0-7 pcie_rp_9_12.asl => To hold RP09-RP12 entries refer as 0:0x1D.0-3 pcie_rp_13_16.asl => To hold RP13-RP16 entries refer as 0:0x1D.4-7
For PCH-H pcie_rp_17_24.asl => To hold RP17-RP24 entries refer as 0:0x1B.0-7
Also create pcie_port.asl for common RP number using PCI configuration space and calling _PRT method from common pci_rp_xx_xx.asl file.
TEST=Able to build and boot CML and TGL platform. 1) Dump and disassemble DSDT, verify RP01-RP12 device present inside common pcie asl is still there for TGL and RP01-RP16 for CML. 2) Verify no ACPI error seen while running 'dmesg` from console.
Signed-off-by: Subrata Banik subrata.banik@intel.com Change-Id: Iaff9decb63ed88eb64c9e61a57d6adf69a46d3d4 --- M src/soc/intel/cannonlake/acpi/pcie.asl R src/soc/intel/common/block/acpi/acpi/pcie_port.asl A src/soc/intel/common/block/acpi/acpi/pcie_rp_13_16.asl A src/soc/intel/common/block/acpi/acpi/pcie_rp_17_24.asl A src/soc/intel/common/block/acpi/acpi/pcie_rp_1_8.asl A src/soc/intel/common/block/acpi/acpi/pcie_rp_9_12.asl M src/soc/intel/denverton_ns/acpi/pcie.asl M src/soc/intel/elkhartlake/acpi/pcie.asl M src/soc/intel/icelake/acpi/pcie.asl M src/soc/intel/jasperlake/acpi/pcie.asl M src/soc/intel/skylake/acpi/pcie.asl M src/soc/intel/tigerlake/acpi/pcie.asl 12 files changed, 217 insertions(+), 1,607 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/46004/1
diff --git a/src/soc/intel/cannonlake/acpi/pcie.asl b/src/soc/intel/cannonlake/acpi/pcie.asl index 302863b..8d3a7cc 100644 --- a/src/soc/intel/cannonlake/acpi/pcie.asl +++ b/src/soc/intel/cannonlake/acpi/pcie.asl @@ -111,413 +111,14 @@ } } } - -Device (RP01) -{ - Name (_ADR, 0x001C0000) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP02) -{ - Name (_ADR, 0x001C0001) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP03) -{ - Name (_ADR, 0x001C0002) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP04) -{ - Name (_ADR, 0x001C0003) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP05) -{ - Name (_ADR, 0x001C0004) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP06) -{ - Name (_ADR, 0x001C0005) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP07) -{ - Name (_ADR, 0x001C0006) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP08) -{ - Name (_ADR, 0x001C0007) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP09) -{ - Name (_ADR, 0x001D0000) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP10) -{ - Name (_ADR, 0x001D0001) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP11) -{ - Name (_ADR, 0x001D0002) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP12) -{ - Name (_ADR, 0x001D0003) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP13) -{ - Name (_ADR, 0x001D0004) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP14) -{ - Name (_ADR, 0x001D0005) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP15) -{ - Name (_ADR, 0x001D0006) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP16) -{ - Name (_ADR, 0x001D0007) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} +/* RP01-RP08 */ +#include <soc/intel/common/block/acpi/acpi/pcie_rp_1_8.asl> +/* RP09-RP12 */ +#include <soc/intel/common/block/acpi/acpi/pcie_rp_9_12.asl> +/* RP13-RP16 */ +#include <soc/intel/common/block/acpi/acpi/pcie_rp_13_16.asl>
#if CONFIG(SOC_INTEL_CANNONLAKE_PCH_H) -Device (RP17) -{ - Name (_ADR, 0x001B0000) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP18) -{ - Name (_ADR, 0x001B0001) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP19) -{ - Name (_ADR, 0x001B0002) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP20) -{ - Name (_ADR, 0x001B0003) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP21) -{ - Name (_ADR, 0x001B0004) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP22) -{ - Name (_ADR, 0x001B0005) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP23) -{ - Name (_ADR, 0x001B0006) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP24) -{ - Name (_ADR, 0x001B0007) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} +/* RP17-RP24 */ +#include <soc/intel/common/block/acpi/acpi/pcie_rp_17_24.asl> #endif diff --git a/src/soc/intel/denverton_ns/acpi/pcie_port.asl b/src/soc/intel/common/block/acpi/acpi/pcie_port.asl similarity index 85% rename from src/soc/intel/denverton_ns/acpi/pcie_port.asl rename to src/soc/intel/common/block/acpi/acpi/pcie_port.asl index d48ecd0..9046eff 100644 --- a/src/soc/intel/denverton_ns/acpi/pcie_port.asl +++ b/src/soc/intel/common/block/acpi/acpi/pcie_port.asl @@ -9,3 +9,8 @@ , 24, RPPN, 8, // Root Port Number } + +Method (_PRT) +{ + Return (IRQM (RPPN)) +} diff --git a/src/soc/intel/common/block/acpi/acpi/pcie_rp_13_16.asl b/src/soc/intel/common/block/acpi/acpi/pcie_rp_13_16.asl new file mode 100644 index 0000000..25be54d --- /dev/null +++ b/src/soc/intel/common/block/acpi/acpi/pcie_rp_13_16.asl @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Device (RP13) +{ + Name (_ADR, 0x001D0004) + + #include "pcie_port.asl" +} + +Device (RP14) +{ + Name (_ADR, 0x001D0005) + + #include "pcie_port.asl" +} + +Device (RP15) +{ + Name (_ADR, 0x001D0006) + + #include "pcie_port.asl" +} + +Device (RP16) +{ + Name (_ADR, 0x001D0007) + + #include "pcie_port.asl" +} diff --git a/src/soc/intel/common/block/acpi/acpi/pcie_rp_17_24.asl b/src/soc/intel/common/block/acpi/acpi/pcie_rp_17_24.asl new file mode 100644 index 0000000..32ef7d1 --- /dev/null +++ b/src/soc/intel/common/block/acpi/acpi/pcie_rp_17_24.asl @@ -0,0 +1,57 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Device (RP17) +{ + Name (_ADR, 0x001B0000) + + #include "pcie_port.asl" +} + +Device (RP18) +{ + Name (_ADR, 0x001B0001) + + #include "pcie_port.asl" +} + +Device (RP19) +{ + Name (_ADR, 0x001B0002) + + #include "pcie_port.asl" +} + +Device (RP20) +{ + Name (_ADR, 0x001B0003) + + #include "pcie_port.asl" +} + +Device (RP21) +{ + Name (_ADR, 0x001B0004) + + #include "pcie_port.asl" +} + +Device (RP22) +{ + Name (_ADR, 0x001B0005) + + #include "pcie_port.asl" +} + +Device (RP23) +{ + Name (_ADR, 0x001B0006) + + #include "pcie_port.asl" +} + +Device (RP24) +{ + Name (_ADR, 0x001B0007) + + #include "pcie_port.asl" +} diff --git a/src/soc/intel/common/block/acpi/acpi/pcie_rp_1_8.asl b/src/soc/intel/common/block/acpi/acpi/pcie_rp_1_8.asl new file mode 100644 index 0000000..f0027f1 --- /dev/null +++ b/src/soc/intel/common/block/acpi/acpi/pcie_rp_1_8.asl @@ -0,0 +1,57 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Device (RP01) +{ + Name (_ADR, 0x001C0000) + + #include "pcie_port.asl" +} + +Device (RP02) +{ + Name (_ADR, 0x001C0001) + + #include "pcie_port.asl" +} + +Device (RP03) +{ + Name (_ADR, 0x001C0002) + + #include "pcie_port.asl" +} + +Device (RP04) +{ + Name (_ADR, 0x001C0003) + + #include "pcie_port.asl" +} + +Device (RP05) +{ + Name (_ADR, 0x001C0004) + + #include "pcie_port.asl" +} + +Device (RP06) +{ + Name (_ADR, 0x001C0005) + + #include "pcie_port.asl" +} + +Device (RP07) +{ + Name (_ADR, 0x001C0006) + + #include "pcie_port.asl" +} + +Device (RP08) +{ + Name (_ADR, 0x001C0007) + + #include "pcie_port.asl" +} diff --git a/src/soc/intel/common/block/acpi/acpi/pcie_rp_9_12.asl b/src/soc/intel/common/block/acpi/acpi/pcie_rp_9_12.asl new file mode 100644 index 0000000..e44e65b --- /dev/null +++ b/src/soc/intel/common/block/acpi/acpi/pcie_rp_9_12.asl @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Device (RP09) +{ + Name (_ADR, 0x001D0000) + + #include "pcie_port.asl" +} + +Device (RP10) +{ + Name (_ADR, 0x001D0001) + + #include "pcie_port.asl" +} + +Device (RP11) +{ + Name (_ADR, 0x001D0002) + + #include "pcie_port.asl" +} + +Device (RP12) +{ + Name (_ADR, 0x001D0003) + + #include "pcie_port.asl" +} diff --git a/src/soc/intel/denverton_ns/acpi/pcie.asl b/src/soc/intel/denverton_ns/acpi/pcie.asl index a34884e..026ecd9 100644 --- a/src/soc/intel/denverton_ns/acpi/pcie.asl +++ b/src/soc/intel/denverton_ns/acpi/pcie.asl @@ -252,94 +252,54 @@ { Name (_ADR, 0x00090000)
- #include "pcie_port.asl" - - Method (_PRT) - { - Return (IRQM (RPPN)) - } + #include <soc/intel/common/block/acpi/acpi/pcie_port.asl> }
Device (RP02) { Name (_ADR, 0x000A0000)
- #include "pcie_port.asl" - - Method (_PRT) - { - Return (IRQM (RPPN)) - } + #include <soc/intel/common/block/acpi/acpi/pcie_port.asl> }
Device (RP03) { Name (_ADR, 0x000B0000)
- #include "pcie_port.asl" - - Method (_PRT) - { - Return (IRQM (RPPN)) - } + #include <soc/intel/common/block/acpi/acpi/pcie_port.asl> }
Device (RP04) { Name (_ADR, 0x000C0000)
- #include "pcie_port.asl" - - Method (_PRT) - { - Return (IRQM (RPPN)) - } + #include <soc/intel/common/block/acpi/acpi/pcie_port.asl> }
Device (RP05) { Name (_ADR, 0x000E0000)
- #include "pcie_port.asl" - - Method (_PRT) - { - Return (IRQM (RPPN)) - } + #include <soc/intel/common/block/acpi/acpi/pcie_port.asl> }
Device (RP06) { Name (_ADR, 0x000F0000)
- #include "pcie_port.asl" - - Method (_PRT) - { - Return (IRQM (RPPN)) - } + #include <soc/intel/common/block/acpi/acpi/pcie_port.asl> }
Device (RP07) { Name (_ADR, 0x00100000)
- #include "pcie_port.asl" - - Method (_PRT) - { - Return (IRQM (RPPN)) - } + #include <soc/intel/common/block/acpi/acpi/pcie_port.asl> }
Device (RP08) { Name (_ADR, 0x00110000)
- #include "pcie_port.asl" - - Method (_PRT) - { - Return (IRQM (RPPN)) - } + #include <soc/intel/common/block/acpi/acpi/pcie_port.asl> } diff --git a/src/soc/intel/elkhartlake/acpi/pcie.asl b/src/soc/intel/elkhartlake/acpi/pcie.asl index a19feb7..586a041 100644 --- a/src/soc/intel/elkhartlake/acpi/pcie.asl +++ b/src/soc/intel/elkhartlake/acpi/pcie.asl @@ -96,206 +96,7 @@ } }
-Device (RP01) -{ - Name (_ADR, 0x001C0000) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP02) -{ - Name (_ADR, 0x001C0001) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP03) -{ - Name (_ADR, 0x001C0002) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP04) -{ - Name (_ADR, 0x001C0003) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP05) -{ - Name (_ADR, 0x001C0004) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP06) -{ - Name (_ADR, 0x001C0005) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP07) -{ - Name (_ADR, 0x001C0006) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP08) -{ - Name (_ADR, 0x001C0007) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP09) -{ - Name (_ADR, 0x001D0000) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP10) -{ - Name (_ADR, 0x001D0001) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP11) -{ - Name (_ADR, 0x001D0002) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP12) -{ - Name (_ADR, 0x001D0003) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} +/* RP01-RP08 */ +#include <soc/intel/common/block/acpi/acpi/pcie_rp_1_8.asl> +/* RP09-RP12 */ +#include <soc/intel/common/block/acpi/acpi/pcie_rp_9_12.asl> diff --git a/src/soc/intel/icelake/acpi/pcie.asl b/src/soc/intel/icelake/acpi/pcie.asl index 9c0933f..b646c42 100644 --- a/src/soc/intel/icelake/acpi/pcie.asl +++ b/src/soc/intel/icelake/acpi/pcie.asl @@ -96,274 +96,9 @@ } }
-Device (RP01) -{ - Name (_ADR, 0x001C0000) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP02) -{ - Name (_ADR, 0x001C0001) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP03) -{ - Name (_ADR, 0x001C0002) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP04) -{ - Name (_ADR, 0x001C0003) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP05) -{ - Name (_ADR, 0x001C0004) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP06) -{ - Name (_ADR, 0x001C0005) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP07) -{ - Name (_ADR, 0x001C0006) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP08) -{ - Name (_ADR, 0x001C0007) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP09) -{ - Name (_ADR, 0x001D0000) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP10) -{ - Name (_ADR, 0x001D0001) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP11) -{ - Name (_ADR, 0x001D0002) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP12) -{ - Name (_ADR, 0x001D0003) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP13) -{ - Name (_ADR, 0x001D0004) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP14) -{ - Name (_ADR, 0x001D0005) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP15) -{ - Name (_ADR, 0x001D0006) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP16) -{ - Name (_ADR, 0x001D0007) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} +/* RP01-RP08 */ +#include <soc/intel/common/block/acpi/acpi/pcie_rp_1_8.asl> +/* RP09-RP12 */ +#include <soc/intel/common/block/acpi/acpi/pcie_rp_9_12.asl> +/* RP13-RP16 */ +#include <soc/intel/common/block/acpi/acpi/pcie_rp_13_16.asl> diff --git a/src/soc/intel/jasperlake/acpi/pcie.asl b/src/soc/intel/jasperlake/acpi/pcie.asl index a19feb7..586a041 100644 --- a/src/soc/intel/jasperlake/acpi/pcie.asl +++ b/src/soc/intel/jasperlake/acpi/pcie.asl @@ -96,206 +96,7 @@ } }
-Device (RP01) -{ - Name (_ADR, 0x001C0000) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP02) -{ - Name (_ADR, 0x001C0001) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP03) -{ - Name (_ADR, 0x001C0002) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP04) -{ - Name (_ADR, 0x001C0003) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP05) -{ - Name (_ADR, 0x001C0004) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP06) -{ - Name (_ADR, 0x001C0005) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP07) -{ - Name (_ADR, 0x001C0006) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP08) -{ - Name (_ADR, 0x001C0007) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP09) -{ - Name (_ADR, 0x001D0000) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP10) -{ - Name (_ADR, 0x001D0001) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP11) -{ - Name (_ADR, 0x001D0002) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP12) -{ - Name (_ADR, 0x001D0003) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} +/* RP01-RP08 */ +#include <soc/intel/common/block/acpi/acpi/pcie_rp_1_8.asl> +/* RP09-RP12 */ +#include <soc/intel/common/block/acpi/acpi/pcie_rp_9_12.asl> diff --git a/src/soc/intel/skylake/acpi/pcie.asl b/src/soc/intel/skylake/acpi/pcie.asl index 6f4aa82f..286f006 100644 --- a/src/soc/intel/skylake/acpi/pcie.asl +++ b/src/soc/intel/skylake/acpi/pcie.asl @@ -96,274 +96,9 @@ } }
-Device (RP01) -{ - Name (_ADR, 0x001C0000) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP02) -{ - Name (_ADR, 0x001C0001) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP03) -{ - Name (_ADR, 0x001C0002) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP04) -{ - Name (_ADR, 0x001C0003) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP05) -{ - Name (_ADR, 0x001C0004) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP06) -{ - Name (_ADR, 0x001C0005) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP07) -{ - Name (_ADR, 0x001C0006) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP08) -{ - Name (_ADR, 0x001C0007) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP09) -{ - Name (_ADR, 0x001D0000) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP10) -{ - Name (_ADR, 0x001D0001) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP11) -{ - Name (_ADR, 0x001D0002) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP12) -{ - Name (_ADR, 0x001D0003) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP13) -{ - Name (_ADR, 0x001D0004) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP14) -{ - Name (_ADR, 0x001D0005) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP15) -{ - Name (_ADR, 0x001D0006) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP16) -{ - Name (_ADR, 0x001D0007) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} +/* RP01-RP08 */ +#include <soc/intel/common/block/acpi/acpi/pcie_rp_1_8.asl> +/* RP09-RP12 */ +#include <soc/intel/common/block/acpi/acpi/pcie_rp_9_12.asl> +/* RP13-RP16 */ +#include <soc/intel/common/block/acpi/acpi/pcie_rp_13_16.asl> diff --git a/src/soc/intel/tigerlake/acpi/pcie.asl b/src/soc/intel/tigerlake/acpi/pcie.asl index a19feb7..9f32b6b 100644 --- a/src/soc/intel/tigerlake/acpi/pcie.asl +++ b/src/soc/intel/tigerlake/acpi/pcie.asl @@ -95,207 +95,7 @@ } } } - -Device (RP01) -{ - Name (_ADR, 0x001C0000) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP02) -{ - Name (_ADR, 0x001C0001) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP03) -{ - Name (_ADR, 0x001C0002) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP04) -{ - Name (_ADR, 0x001C0003) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP05) -{ - Name (_ADR, 0x001C0004) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP06) -{ - Name (_ADR, 0x001C0005) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP07) -{ - Name (_ADR, 0x001C0006) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP08) -{ - Name (_ADR, 0x001C0007) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP09) -{ - Name (_ADR, 0x001D0000) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP10) -{ - Name (_ADR, 0x001D0001) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP11) -{ - Name (_ADR, 0x001D0002) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP12) -{ - Name (_ADR, 0x001D0003) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} +/* RP01-RP08 */ +#include <soc/intel/common/block/acpi/acpi/pcie_rp_1_8.asl> +/* RP09-RP12 */ +#include <soc/intel/common/block/acpi/acpi/pcie_rp_9_12.asl>
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46004 )
Change subject: soc/intel/common/block/acpi: Factor out common pcie_rp_xx_xx.asl ......................................................................
Patch Set 1: Code-Review+1
IMHO, this would be best done using a SSDT generator for the enabled PCIe ports only.
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46004 )
Change subject: soc/intel/common/block/acpi: Factor out common pcie_rp_xx_xx.asl ......................................................................
Patch Set 1:
Patch Set 1: Code-Review+1
IMHO, this would be best done using a SSDT generator for the enabled PCIe ports only.
Yes, totally agree, i will raise a task for internal team to pick and do that going forward. bt i believe for now, this is what look best in terms of reuse of code :) but would be great to generate code based on existing Kconfig option from C code in future.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46004 )
Change subject: soc/intel/common/block/acpi: Factor out common pcie_rp_xx_xx.asl ......................................................................
Patch Set 1:
Patch Set 1:
Patch Set 1: Code-Review+1
IMHO, this would be best done using a SSDT generator for the enabled PCIe ports only.
Yes, totally agree, i will raise a task for internal team to pick and do that going forward. bt i believe for now, this is what look best in terms of reuse of code :) but would be great to generate code based on existing Kconfig option from C code in future.
Not just Kconfig, but also depending on the state of devices at runtime. Why have 24 PCIe root ports in ACPI tables when only 2 of them are present?
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46004 )
Change subject: soc/intel/common/block/acpi: Factor out common pcie_rp_xx_xx.asl ......................................................................
Patch Set 1:
Patch Set 1:
Patch Set 1:
Patch Set 1: Code-Review+1
IMHO, this would be best done using a SSDT generator for the enabled PCIe ports only.
Yes, totally agree, i will raise a task for internal team to pick and do that going forward. bt i believe for now, this is what look best in terms of reuse of code :) but would be great to generate code based on existing Kconfig option from C code in future.
Not just Kconfig, but also depending on the state of devices at runtime. Why have 24 PCIe root ports in ACPI tables when only 2 of them are present?
Aah, that way, true.
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46004 )
Change subject: soc/intel/common/block/acpi: Factor out common pcie_rp_xx_xx.asl ......................................................................
Patch Set 1:
Patch Set 1:
Patch Set 1:
Patch Set 1:
Patch Set 1: Code-Review+1
IMHO, this would be best done using a SSDT generator for the enabled PCIe ports only.
Yes, totally agree, i will raise a task for internal team to pick and do that going forward. bt i believe for now, this is what look best in terms of reuse of code :) but would be great to generate code based on existing Kconfig option from C code in future.
Not just Kconfig, but also depending on the state of devices at runtime. Why have 24 PCIe root ports in ACPI tables when only 2 of them are present?
Aah, that way, true.
if you want, we could park this CL as well, i just want to share that i have tried my best to address the possible common code 😊 before adding ADL ACPI code
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46004 )
Change subject: soc/intel/common/block/acpi: Factor out common pcie_rp_xx_xx.asl ......................................................................
Patch Set 1:
Patch Set 1:
Patch Set 1:
Patch Set 1:
Patch Set 1:
Patch Set 1: Code-Review+1
IMHO, this would be best done using a SSDT generator for the enabled PCIe ports only.
Yes, totally agree, i will raise a task for internal team to pick and do that going forward. bt i believe for now, this is what look best in terms of reuse of code :) but would be great to generate code based on existing Kconfig option from C code in future.
Not just Kconfig, but also depending on the state of devices at runtime. Why have 24 PCIe root ports in ACPI tables when only 2 of them are present?
Aah, that way, true.
if you want, we could park this CL as well, i just want to share that i have tried my best to address the possible common code 😊 before adding ADL ACPI code
I'd park it for now. It's quite large...
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46004 )
Change subject: soc/intel/common/block/acpi: Factor out common pcie_rp_xx_xx.asl ......................................................................
Patch Set 1:
Patch Set 1:
Patch Set 1:
Patch Set 1:
Patch Set 1:
Patch Set 1:
Patch Set 1: Code-Review+1
IMHO, this would be best done using a SSDT generator for the enabled PCIe ports only.
Yes, totally agree, i will raise a task for internal team to pick and do that going forward. bt i believe for now, this is what look best in terms of reuse of code :) but would be great to generate code based on existing Kconfig option from C code in future.
Not just Kconfig, but also depending on the state of devices at runtime. Why have 24 PCIe root ports in ACPI tables when only 2 of them are present?
Aah, that way, true.
if you want, we could park this CL as well, i just want to share that i have tried my best to address the possible common code 😊 before adding ADL ACPI code
I'd park it for now. It's quite large...
Sure, then i will rebase ADL CL base on last +2'ed code in this trend
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Angel Pons (Code Review) -
Subrata Banik (Code Review)