Change in coreboot[master]: [DNM] soc/intel: Fix SPI write protect and EISS support - coreboot-gerrit

14 Feb 2021


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Benjamin Doron has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50724 )
Change subject: [DNM] soc/intel: Fix SPI write protect and EISS support
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Patch Set 3:
(1 comment)
File src/soc/intel/common/block/include/intelblocks/msr.h:
https://review.coreboot.org/c/coreboot/+/50724/comment/42ba6d6d_36cade08 
PS3, Line 54: Defined for Skylake and Cannonlake
TODO: Is it architectural?
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ice2fb1a049fe24a8e4149a52016a62dadd7a3404
Gerrit-Change-Number: 50724
Gerrit-PatchSet: 3
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