[M] Change in coreboot[master]: soc/amd/mendocino: Enhance DPTC_INPUT to support 13 DPTC thermal para...

[Chris Wang (Code Review)]

Attention is currently required from: Jason Glenesk, Raul Rangel, Jason Nien, EricKY Cheng, Matt DeVillier, Martin Roth, Tim Van Patten, Fred Reitberger, Felix Held.

Chris Wang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68649 )

Change subject: soc/amd/mendocino: Enhance DPTC_INPUT to support 13 DPTC thermal parameters
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Patch Set 31:

(1 comment)

File src/soc/amd/mendocino/root_complex.c:

https://review.coreboot.org/c/coreboot/+/68649/comment/7b0b0231_4285d71f 
PS16, Line 393: #else
> I don't fully understand what this means. What is "AMD IRM"?

The document name is "Infrastructure Roadmap (IRM) for FT6 Processors" (doc#57316)

You can find the details about the thermal/power parameter informations in that document.

DPTC is to change the those settings to SMU via ALIB. so it will only change the value which you input. Keep setting alignment will be good.