Aaron Durbin (adurbin@chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13936
-gerrit
commit 978f8cb20de2b8d276d026a5e615e7b84a23d5e3 Author: Aaron Durbin adurbin@chromium.org Date: Mon Mar 7 16:23:47 2016 -0600
x86 chipsets: utilize x86_setup_mtrrs_with_detect()
For all the chipsets which were performing the following sequence: x86_setup_fixed_mtrrs(); x86_setup_var_mtrrs(cpuid_eax(0x80000008) & 0xff, 2);
Replace that with x86_setup_mtrrs_with_detect() since it is equivalent.
Change-Id: I9f362dbf38942d675f615d22b9e5770ce65e5a08 Signed-off-by: Aaron Durbin adurbin@chromium.org --- src/cpu/intel/fsp_model_206ax/model_206ax_init.c | 5 +---- src/cpu/intel/haswell/haswell_init.c | 3 +-- src/cpu/intel/model_2065x/model_2065x_init.c | 5 +---- src/cpu/intel/model_206ax/model_206ax_init.c | 5 +---- src/soc/intel/baytrail/cpu.c | 3 +-- src/soc/intel/braswell/cpu.c | 3 +-- src/soc/intel/broadwell/cpu.c | 3 +-- src/soc/intel/skylake/cpu.c | 3 +-- 8 files changed, 8 insertions(+), 22 deletions(-)
diff --git a/src/cpu/intel/fsp_model_206ax/model_206ax_init.c b/src/cpu/intel/fsp_model_206ax/model_206ax_init.c index f6e352e..da1ea2b 100644 --- a/src/cpu/intel/fsp_model_206ax/model_206ax_init.c +++ b/src/cpu/intel/fsp_model_206ax/model_206ax_init.c @@ -366,7 +366,6 @@ static void intel_cores_init(struct device *cpu) static void model_206ax_init(struct device *cpu) { char processor_name[49]; - struct cpuid_result cpuid_regs;
/* Turn on caching if we haven't already */ x86_enable_cache(); @@ -381,9 +380,7 @@ static void model_206ax_init(struct device *cpu) printk(BIOS_INFO, "CPU: %s.\n", processor_name);
/* Setup MTRRs based on physical address size */ - cpuid_regs = cpuid(0x80000008); - x86_setup_fixed_mtrrs(); - x86_setup_var_mtrrs(cpuid_regs.eax & 0xff, 2); + x86_setup_mtrrs_with_detect(); x86_mtrr_check();
/* Setup Page Attribute Tables (PAT) */ diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c index 5c34a30..b4bff83 100644 --- a/src/cpu/intel/haswell/haswell_init.c +++ b/src/cpu/intel/haswell/haswell_init.c @@ -717,8 +717,7 @@ static void configure_mca(void) static void bsp_init_before_ap_bringup(struct bus *cpu_bus) { /* Setup MTRRs based on physical address size. */ - x86_setup_fixed_mtrrs(); - x86_setup_var_mtrrs(cpuid_eax(0x80000008) & 0xff, 2); + x86_setup_mtrrs_with_detect(); x86_mtrr_check();
initialize_vr_config(); diff --git a/src/cpu/intel/model_2065x/model_2065x_init.c b/src/cpu/intel/model_2065x/model_2065x_init.c index d724842..4005b3d 100644 --- a/src/cpu/intel/model_2065x/model_2065x_init.c +++ b/src/cpu/intel/model_2065x/model_2065x_init.c @@ -358,7 +358,6 @@ static void intel_cores_init(struct device *cpu) static void model_2065x_init(struct device *cpu) { char processor_name[49]; - struct cpuid_result cpuid_regs;
/* Turn on caching if we haven't already */ x86_enable_cache(); @@ -374,9 +373,7 @@ static void model_2065x_init(struct device *cpu) printk(BIOS_INFO, "CPU:lapic=%ld, boot_cpu=%d\n", lapicid (), boot_cpu ());
/* Setup MTRRs based on physical address size */ - cpuid_regs = cpuid(0x80000008); - x86_setup_fixed_mtrrs(); - x86_setup_var_mtrrs(cpuid_regs.eax & 0xff, 2); + x86_setup_mtrrs_with_detect(); x86_mtrr_check();
/* Setup Page Attribute Tables (PAT) */ diff --git a/src/cpu/intel/model_206ax/model_206ax_init.c b/src/cpu/intel/model_206ax/model_206ax_init.c index ae2332e4..7575603 100644 --- a/src/cpu/intel/model_206ax/model_206ax_init.c +++ b/src/cpu/intel/model_206ax/model_206ax_init.c @@ -552,7 +552,6 @@ static void intel_cores_init(struct device *cpu) static void model_206ax_init(struct device *cpu) { char processor_name[49]; - struct cpuid_result cpuid_regs;
/* Turn on caching if we haven't already */ x86_enable_cache(); @@ -567,9 +566,7 @@ static void model_206ax_init(struct device *cpu) printk(BIOS_INFO, "CPU: %s.\n", processor_name);
/* Setup MTRRs based on physical address size */ - cpuid_regs = cpuid(0x80000008); - x86_setup_fixed_mtrrs(); - x86_setup_var_mtrrs(cpuid_regs.eax & 0xff, 2); + x86_setup_mtrrs_with_detect(); x86_mtrr_check();
/* Setup Page Attribute Tables (PAT) */ diff --git a/src/soc/intel/baytrail/cpu.c b/src/soc/intel/baytrail/cpu.c index 9c69d16..6188689 100644 --- a/src/soc/intel/baytrail/cpu.c +++ b/src/soc/intel/baytrail/cpu.c @@ -83,8 +83,7 @@ void baytrail_init_cpus(device_t dev) void *default_smm_area;
/* Set up MTRRs based on physical address size. */ - x86_setup_fixed_mtrrs(); - x86_setup_var_mtrrs(pattrs->address_bits, 2); + x86_setup_mtrrs_with_detect(); x86_mtrr_check();
mp_params.num_cpus = pattrs->num_cpus, diff --git a/src/soc/intel/braswell/cpu.c b/src/soc/intel/braswell/cpu.c index feb9d9b..71af487 100644 --- a/src/soc/intel/braswell/cpu.c +++ b/src/soc/intel/braswell/cpu.c @@ -89,8 +89,7 @@ void soc_init_cpus(device_t dev) __FILE__, __func__, dev_name(dev));
/* Set up MTRRs based on physical address size. */ - x86_setup_fixed_mtrrs(); - x86_setup_var_mtrrs(pattrs->address_bits, 2); + x86_setup_mtrrs_with_detect(); x86_mtrr_check();
mp_params.num_cpus = pattrs->num_cpus, diff --git a/src/soc/intel/broadwell/cpu.c b/src/soc/intel/broadwell/cpu.c index 4a94c1d..5f3fb15 100644 --- a/src/soc/intel/broadwell/cpu.c +++ b/src/soc/intel/broadwell/cpu.c @@ -573,8 +573,7 @@ static void configure_mca(void) static void bsp_init_before_ap_bringup(struct bus *cpu_bus) { /* Setup MTRRs based on physical address size. */ - x86_setup_fixed_mtrrs(); - x86_setup_var_mtrrs(cpuid_eax(0x80000008) & 0xff, 2); + x86_setup_mtrrs_with_detect(); x86_mtrr_check();
initialize_vr_config(); diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c index 327bee9..d154f0e 100644 --- a/src/soc/intel/skylake/cpu.c +++ b/src/soc/intel/skylake/cpu.c @@ -343,8 +343,7 @@ static void configure_mca(void) static void bsp_init_before_ap_bringup(struct bus *cpu_bus) { /* Setup MTRRs based on physical address size. */ - x86_setup_fixed_mtrrs(); - x86_setup_var_mtrrs(cpuid_eax(0x80000008) & 0xff, 2); + x86_setup_mtrrs_with_detect(); x86_mtrr_check(); }
-
Aaron Durbin