Shaunak Saha has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37427 )
Change subject: soc/intel/tigerlake: Update GPIO config ......................................................................
Patch Set 16:
(2 comments)
Patch Set 16:
This CL should really be split into 4 changes:
a) Changes for GPP_* and PMC_GPP_* that are done in gpio.c(soc_pmc_gpio_routes), gpio_soc_defs.h(GPP_* definitions) and pmc.h -- This is really fixing the GPIO group mapping to GPE. b) Changes for matching GPIO community/group mapping in coreboot with that of the latest kernel driver -- This should include changes in gpio.asl to add GCM0, GCM1, GCM4, GCM5 and the changes in GADD. Changes in gpio.c. Changes in gpio.h. Changes in gpio_defs.h. Changes in gpio_soc_defs.h except the pinmux macros. c) Changes for adding ASL routines for GPIO(GTXS, STXS, CTXS) and updating GRXS. d) Changes for pinmux -- Ideally I don't think this is required. But, if we do, then this should be a separate change.
Got it. Will split into 4 patches.
https://review.coreboot.org/c/coreboot/+/37427/16/src/soc/intel/tigerlake/ac... File src/soc/intel/tigerlake/acpi/gpio.asl:
https://review.coreboot.org/c/coreboot/+/37427/16/src/soc/intel/tigerlake/ac... PS16, Line 20: Device (GPIO)
So, I was looking at the latest version of pinctrl-tigerlake. […]
Got it. So with this it should be pins for every community listed as INT34C5:0<0-5>
https://review.coreboot.org/c/coreboot/+/37427/16/src/soc/intel/tigerlake/in... File src/soc/intel/tigerlake/include/soc/gpio.h:
https://review.coreboot.org/c/coreboot/+/37427/16/src/soc/intel/tigerlake/in... PS16, Line 22: CROS_GPIO_DEVICE_NAME
This will have to be provided for each community device as per the comment on gpio.asl file.
Ack