[S] Change in coreboot[master]: soc/intel/xeon_sp/spr: Drop devicetree setting X2apic

[Patrick Rudolph (Code Review)]

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74185 )

Change subject: soc/intel/xeon_sp/spr: Drop devicetree setting X2apic
......................................................................

soc/intel/xeon_sp/spr: Drop devicetree setting X2apic

Drop devicetree setting X2apic as the same functionality is already
exposed in Kconfig.

To activate X2apic select X2APIC_ONLY or X2APIC_RUNTIME in
the "APIC operation mode".

Note: Your OS must have support for X2APIC. If you are using less
      than 256 CPU cores select XAPIC_ONLY here.

Test:
- Booted to OS in X2APIC mode when X2APIC_ONLY or X2APIC_RUNTIME
  was selected.
- Booted to OS in XAPIC mode when XAPIC_ONLY was selected.

Change-Id: I65152b0696a45b62a5629fd95801187354c7a93b
Signed-off-by: Patrick Rudolph 
---
M src/soc/intel/xeon_sp/spr/chip.h
M src/soc/intel/xeon_sp/spr/romstage.c
2 files changed, 26 insertions(+), 6 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/74185/1

diff --git a/src/soc/intel/xeon_sp/spr/chip.h b/src/soc/intel/xeon_sp/spr/chip.h
index 5144372..28af550 100644
--- a/src/soc/intel/xeon_sp/spr/chip.h
+++ b/src/soc/intel/xeon_sp/spr/chip.h
@@ -46,7 +46,6 @@
    uint32_t pstate_req_ratio;

uint8_t vtd_support;
-	uint8_t x2apic;

/* Generic IO decode ranges */
    uint32_t gen1_dec;
diff --git a/src/soc/intel/xeon_sp/spr/romstage.c b/src/soc/intel/xeon_sp/spr/romstage.c
index f4eae9c..051a055 100644
--- a/src/soc/intel/xeon_sp/spr/romstage.c
+++ b/src/soc/intel/xeon_sp/spr/romstage.c
@@ -159,11 +159,8 @@

m_cfg->BoardTypeBitmask = 0x11111133;

-	m_cfg->X2apic = config->x2apic;
-
-	printk(BIOS_INFO, "m_cfg->X2apic = 0x%x  config->x2apic = 0x%x\n", m_cfg->X2apic,
-	       config->x2apic);
-
+	/* Let coreboot configure LAPIC based on Kconfig */
+	m_cfg->X2apic = 0;

m_cfg->serialDebugMsgLvl = 0x3;