Attention is currently required from: Lance Zhao, Maulik V Vaghela, Paul Menzel, Meera Ravindranath, Subrata Banik, Archana Patni, Michael Niewöhner, Ronak Kanabar. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59790 )
Change subject: mb/google/brya: Fix S0i3 regression ......................................................................
Patch Set 2: Code-Review+1
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/59790/comment/3b04ebe4_73bab76b PS2, Line 8:
Please describe the problem. […]
When entering S0ix states, when the PM timer is enabled, the system is unable to enter S0i3 (PM timer off is required for S0i3 entry).
https://review.coreboot.org/c/coreboot/+/59790/comment/1d81c90c_e1d9ddbc PS2, Line 9: ACPI PM timer needs to be disabled explicitly in CB to increment S0i3 : counter as FSP has no control to do the same since suggestion: I would state this more like
``` Keeping the PM timer being enabled will disqualify an ADL system from entering S0i3, and will also cause an increase in power during suspend states. The PM timer is not required for brya boards, therefore disable it. ```
https://review.coreboot.org/c/coreboot/+/59790/comment/5d1abb28_23347587 PS2, Line 14: TEST=Boot gimble to OS and verify S0i3 counter incrementing
How can this be verified?
After exiting S0ix suspend state, `cat /sys/kernel/debug/pmc_core/substate_residencies` will show S0i3 residency and not S0i2
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Tim Wawrzynczak (Code Review)