Change in coreboot[master]: mb/intel/jslrvp: Update the sleep assertion widths and Power Cycle Du...

[V Sowmya (Code Review)]

V Sowmya has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43793 )

Change subject: mb/intel/jslrvp: Update the sleep assertion widths and Power Cycle Duration
......................................................................

mb/intel/jslrvp: Update the sleep assertion widths and Power Cycle Duration

This patch updates the SLP_X assertion width and Power Cycle Duration
for the Japerlake RVP.

BUG=b:159104150

Change-Id: Ie2a8d959d7ebbf9c24f8c4e8d5c68b70e0ac5708
Signed-off-by: V Sowmya 
---
M src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb
1 file changed, 14 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/43793/1

diff --git a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb
index 616e35c..8b39d51 100644
--- a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb
+++ b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb
@@ -154,6 +154,20 @@
                 },
    }"

+	/* Set the minimum assertion width */
+	register "PchPmSlpS3MinAssert"  = "3"  # 50ms
+	register "PchPmSlpS4MinAssert"  = "1"  # 1s
+	register "PchPmSlpSusMinAssert" = "3"  # 1s
+	register "PchPmSlpAMinAssert"   = "3"  # 98ms
+
+	# NOTE: Duration programmed in the below register should never be smaller than the
+	# stretch duration programmed in the following registers -
+	#       - GEN_PMCON_A.SLP_S3_MIN_ASST_WDTH (PchPmSlpS3MinAssert)
+	#       - GEN_PMCON_A.S4MAW (PchPmSlpS4MinAssert)
+	#       - PM_CFG.SLP_A_MIN_ASST_WDTH (PchPmSlpAMinAssert)
+	#       - PM_CFG.SLP_LAN_MIN_ASST_WDTH
+	register "PchPmPwrCycDur" = "1"       # 1s
+
    device domain 0 on
    	device pci 00.0 on  end # Host Bridge
    	device pci 02.0 on  end # Integrated Graphics Device

[V Sowmya (Code Review)]

Hello build bot (Jenkins), Furquan Shaikh, Jamie Chen, Maulik V Vaghela, Rizwan Qureshi, Sridhar Siricilla, Krishna P Bhat D, Aamir Bohra, Karthik Ramasubramanian,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/43793

to look at the new patch set (#2).

Change subject: mb/intel/jslrvp: Update the sleep assertion widths and Power Cycle Duration
......................................................................

mb/intel/jslrvp: Update the sleep assertion widths and Power Cycle Duration

This patch updates the SLP_X assertion width and Power Cycle Duration
for the Japerlake RVP.

BUG=b:159104150

Change-Id: Ie2a8d959d7ebbf9c24f8c4e8d5c68b70e0ac5708
Signed-off-by: V Sowmya 
---
M src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb
1 file changed, 14 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/43793/2

[Sridhar Siricilla (Code Review)]

Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43793 )

Change subject: mb/intel/jslrvp: Update the sleep assertion widths and Power Cycle Duration
......................................................................

Patch Set 3:

(1 comment)

https://review.coreboot.org/c/coreboot/+/43793/3//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/43793/3//COMMIT_MSG@7 
PS3, Line 7:  
signal

Change in coreboot[master]: mb/intel/jslrvp: Update SLP_Sx assertion widths and PwrCycDur

[V Sowmya (Code Review)]

Hello build bot (Jenkins), Furquan Shaikh, Jamie Chen, Maulik V Vaghela, Rizwan Qureshi, Sridhar Siricilla, Krishna P Bhat D, Aamir Bohra, Karthik Ramasubramanian,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/43793

to look at the new patch set (#4).

Change subject: mb/intel/jslrvp: Update SLP_Sx assertion widths and PwrCycDur
......................................................................

mb/intel/jslrvp: Update SLP_Sx assertion widths and PwrCycDur

This patch updates the SLP_Sx assertion widths and power cycle duration
for the Japerlake RVP.

Power cycle duration:
With default value,
     S0->S5 -> [ ~4.2 seconds delay ] -> S5->S0

With value set to 1,
     S0->S5 -> [ ~1.2 seconds delay ] -> S5->S0

BUG=b:159104150
TEST=Verified it on JSLRVP.

Change-Id: Ie2a8d959d7ebbf9c24f8c4e8d5c68b70e0ac5708
Signed-off-by: V Sowmya 
---
M src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb
1 file changed, 14 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/43793/4

Change in coreboot[master]: mb/intel/jslrvp: Update SLP_Sx assertion widths and PwrCycDur

[V Sowmya (Code Review)]

V Sowmya has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43793 )

Change subject: mb/intel/jslrvp: Update SLP_Sx assertion widths and PwrCycDur
......................................................................

Patch Set 4:

(1 comment)

https://review.coreboot.org/c/coreboot/+/43793/3//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/43793/3//COMMIT_MSG@7 
PS3, Line 7:
> signal

Done

Change in coreboot[master]: mb/intel/jslrvp: Update SLP_Sx assertion widths and PwrCycDur

[Sridhar Siricilla (Code Review)]

Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43793 )

Change subject: mb/intel/jslrvp: Update SLP_Sx assertion widths and PwrCycDur
......................................................................

Patch Set 4: Code-Review+1

Change in coreboot[master]: mb/intel/jslrvp: Update SLP_Sx assertion widths and PwrCycDur

[V Sowmya (Code Review)]

Hello build bot (Jenkins), Furquan Shaikh, Jamie Chen, Maulik V Vaghela, Rizwan Qureshi, Sridhar Siricilla, Krishna P Bhat D, Aamir Bohra, Karthik Ramasubramanian,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/43793

to look at the new patch set (#5).

Change subject: mb/intel/jslrvp: Update SLP_Sx assertion widths and PwrCycDur
......................................................................

mb/intel/jslrvp: Update SLP_Sx assertion widths and PwrCycDur

This patch updates the SLP_Sx assertion widths and power cycle duration
for the Japerlake RVP.

Power cycle duration:
With default value,
     S0->S5 -> [ ~4.2 seconds delay ] -> S5->S0

With value set to 1,
     S0->S5 -> [ ~1.2 seconds delay ] -> S5->S0

BUG=b:159104150
TEST=Verified that the power cycle duration is ~1.2s with global
         reset on JSLRVP.

Change-Id: Ie2a8d959d7ebbf9c24f8c4e8d5c68b70e0ac5708
Signed-off-by: V Sowmya 
---
M src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb
1 file changed, 14 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/43793/5

Change in coreboot[master]: mb/intel/jslrvp: Update SLP_Sx assertion widths and PwrCycDur

[Sridhar Siricilla (Code Review)]

Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43793 )

Change subject: mb/intel/jslrvp: Update SLP_Sx assertion widths and PwrCycDur
......................................................................

Patch Set 5: Code-Review+1

Change in coreboot[master]: mb/intel/jslrvp: Update SLP_Sx assertion widths and PwrCycDur

[Ronak Kanabar (Code Review)]

Ronak Kanabar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43793 )

Change subject: mb/intel/jslrvp: Update SLP_Sx assertion widths and PwrCycDur
......................................................................

Patch Set 5: Code-Review+1

Change in coreboot[master]: mb/intel/jslrvp: Update SLP_Sx assertion widths and PwrCycDur

[Aamir Bohra (Code Review)]

Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43793 )

Change subject: mb/intel/jslrvp: Update SLP_Sx assertion widths and PwrCycDur
......................................................................

Patch Set 5: Code-Review+2

Change in coreboot[master]: mb/intel/jslrvp: Update SLP_Sx assertion widths and PwrCycDur

[Subrata Banik (Code Review)]

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43793 )

Change subject: mb/intel/jslrvp: Update SLP_Sx assertion widths and PwrCycDur
......................................................................

Patch Set 5: Code-Review+2

Change in coreboot[master]: mb/intel/jslrvp: Update SLP_Sx assertion widths and PwrCycDur

[Subrata Banik (Code Review)]

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/43793 )

Change subject: mb/intel/jslrvp: Update SLP_Sx assertion widths and PwrCycDur
......................................................................

mb/intel/jslrvp: Update SLP_Sx assertion widths and PwrCycDur

This patch updates the SLP_Sx assertion widths and power cycle duration
for the Japerlake RVP.

Power cycle duration:
With default value,
     S0->S5 -> [ ~4.2 seconds delay ] -> S5->S0

With value set to 1,
     S0->S5 -> [ ~1.2 seconds delay ] -> S5->S0

BUG=b:159104150
TEST=Verified that the power cycle duration is ~1.2s with global
         reset on JSLRVP.

Change-Id: Ie2a8d959d7ebbf9c24f8c4e8d5c68b70e0ac5708
Signed-off-by: V Sowmya 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43793
Tested-by: build bot (Jenkins) 
Reviewed-by: Sridhar Siricilla 
Reviewed-by: Ronak Kanabar 
Reviewed-by: Aamir Bohra 
Reviewed-by: Subrata Banik 
---
M src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb
1 file changed, 14 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Subrata Banik: Looks good to me, approved
  Aamir Bohra: Looks good to me, approved
  Ronak Kanabar: Looks good to me, but someone else must approve
  Sridhar Siricilla: Looks good to me, but someone else must approve

diff --git a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb
index 1681b71..c5a3fc30 100644
--- a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb
+++ b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb
@@ -154,6 +154,20 @@
    	},
    }"

+	# Set the minimum assertion width
+	register "PchPmSlpS3MinAssert"  = "3"  # 50ms
+	register "PchPmSlpS4MinAssert"  = "1"  # 1s
+	register "PchPmSlpSusMinAssert" = "3"  # 1s
+	register "PchPmSlpAMinAssert"   = "3"  # 98ms
+
+	# NOTE: Duration programmed in the below register should never be smaller than the
+	# stretch duration programmed in the following registers -
+	#       - GEN_PMCON_A.SLP_S3_MIN_ASST_WDTH (PchPmSlpS3MinAssert)
+	#       - GEN_PMCON_A.S4MAW (PchPmSlpS4MinAssert)
+	#       - PM_CFG.SLP_A_MIN_ASST_WDTH (PchPmSlpAMinAssert)
+	#       - PM_CFG.SLP_LAN_MIN_ASST_WDTH
+	register "PchPmPwrCycDur" = "1"       # 1s
+
    device domain 0 on
    	device pci 00.0 on  end # Host Bridge
    	device pci 02.0 on  end # Integrated Graphics Device