Jonathan Zhang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43982 )
Change subject: soc/intel/xeon_sp: update DIMM_MAX and DIMM_SPD_SIZE ......................................................................
soc/intel/xeon_sp: update DIMM_MAX and DIMM_SPD_SIZE
SKX-SP and CPX-SP processors have 2 IMC, there are 3 channels per IMC, 2 DIMMs per channel.
They support DDR4.
Set DIMM_MAX and DIMM_SPD_SIZE accordingly.
Change-Id: I66cc512465362d5ba04dc36534360c94ca23e77a Signed-off-by: Jonathan Zhang jonzhang@fb.com --- M src/soc/intel/xeon_sp/Kconfig 1 file changed, 10 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/43982/1
diff --git a/src/soc/intel/xeon_sp/Kconfig b/src/soc/intel/xeon_sp/Kconfig index b410dec..cb0a589 100644 --- a/src/soc/intel/xeon_sp/Kconfig +++ b/src/soc/intel/xeon_sp/Kconfig @@ -103,4 +103,14 @@ hex default 0x80000
+# 2 IMCs, 3 channel per IMC, 2 DIMMs per channel +config DIMM_MAX + int + default 12 + +# DDR4 +config DIMM_SPD_SIZE + int + default 512 + endif ## SOC_INTEL_XEON_SP
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43982 )
Change subject: soc/intel/xeon_sp: update DIMM_MAX and DIMM_SPD_SIZE ......................................................................
Patch Set 1: Code-Review+1
(1 comment)
https://review.coreboot.org/c/coreboot/+/43982/1/src/soc/intel/xeon_sp/Kconf... File src/soc/intel/xeon_sp/Kconfig:
https://review.coreboot.org/c/coreboot/+/43982/1/src/soc/intel/xeon_sp/Kconf... PS1, Line 109: 12 That's for a single processor, though. What about multi-socket platforms?
Hello build bot (Jenkins), Angel Pons, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/43982
to look at the new patch set (#2).
Change subject: soc/intel/xeon_sp/cpx: configure DIMM_MAX and DIMM_SPD_SIZE ......................................................................
soc/intel/xeon_sp/cpx: configure DIMM_MAX and DIMM_SPD_SIZE
CPX-SP processor has 2 IMC, there are 3 channels per IMC, 2 DIMMs per channel.
It supports DDR4.
Configure default values for DIMM_MAX and DIMM_SPD_SIZE accordingly.
Change-Id: I66cc512465362d5ba04dc36534360c94ca23e77a Signed-off-by: Jonathan Zhang jonzhang@fb.com --- M src/soc/intel/xeon_sp/cpx/Kconfig 1 file changed, 11 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/43982/2
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43982 )
Change subject: soc/intel/xeon_sp/cpx: configure DIMM_MAX and DIMM_SPD_SIZE ......................................................................
Patch Set 2: Code-Review+1
(2 comments)
https://review.coreboot.org/c/coreboot/+/43982/1/src/soc/intel/xeon_sp/Kconf... File src/soc/intel/xeon_sp/Kconfig:
https://review.coreboot.org/c/coreboot/+/43982/1/src/soc/intel/xeon_sp/Kconf... PS1, Line 109: 12
That's for a single processor, though. […]
We can handle that later
https://review.coreboot.org/c/coreboot/+/43982/2/src/soc/intel/xeon_sp/cpx/K... File src/soc/intel/xeon_sp/cpx/Kconfig:
https://review.coreboot.org/c/coreboot/+/43982/2/src/soc/intel/xeon_sp/cpx/K... PS2, Line 75: 6 This was 12 on the previous patchset
Jonathan Zhang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43982 )
Change subject: soc/intel/xeon_sp/cpx: configure DIMM_MAX and DIMM_SPD_SIZE ......................................................................
Patch Set 2:
(2 comments)
Thanks!
https://review.coreboot.org/c/coreboot/+/43982/1/src/soc/intel/xeon_sp/Kconf... File src/soc/intel/xeon_sp/Kconfig:
https://review.coreboot.org/c/coreboot/+/43982/1/src/soc/intel/xeon_sp/Kconf... PS1, Line 109: 12
That's for a single processor, though. […]
Thank you for the comment. I made another PR to configure DIMM_MAX in mainboard code.
https://review.coreboot.org/c/coreboot/+/43982/2/src/soc/intel/xeon_sp/cpx/K... File src/soc/intel/xeon_sp/cpx/Kconfig:
https://review.coreboot.org/c/coreboot/+/43982/2/src/soc/intel/xeon_sp/cpx/K... PS2, Line 75: 6
This was 12 on the previous patchset
Done
Hello build bot (Jenkins), Angel Pons, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/43982
to look at the new patch set (#3).
Change subject: soc/intel/xeon_sp/cpx: configure DIMM_MAX and DIMM_SPD_SIZE ......................................................................
soc/intel/xeon_sp/cpx: configure DIMM_MAX and DIMM_SPD_SIZE
CPX-SP processor has 2 IMC, there are 3 channels per IMC, 2 DIMMs per channel.
It supports DDR4.
Configure default values for DIMM_MAX and DIMM_SPD_SIZE accordingly.
Change-Id: I66cc512465362d5ba04dc36534360c94ca23e77a Signed-off-by: Jonathan Zhang jonzhang@fb.com --- M src/soc/intel/xeon_sp/cpx/Kconfig 1 file changed, 11 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/43982/3
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43982 )
Change subject: soc/intel/xeon_sp/cpx: configure DIMM_MAX and DIMM_SPD_SIZE ......................................................................
Patch Set 3: Code-Review+2
Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/43982 )
Change subject: soc/intel/xeon_sp/cpx: configure DIMM_MAX and DIMM_SPD_SIZE ......................................................................
soc/intel/xeon_sp/cpx: configure DIMM_MAX and DIMM_SPD_SIZE
CPX-SP processor has 2 IMC, there are 3 channels per IMC, 2 DIMMs per channel.
It supports DDR4.
Configure default values for DIMM_MAX and DIMM_SPD_SIZE accordingly.
Change-Id: I66cc512465362d5ba04dc36534360c94ca23e77a Signed-off-by: Jonathan Zhang jonzhang@fb.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/43982 Reviewed-by: Angel Pons th3fanbus@gmail.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/soc/intel/xeon_sp/cpx/Kconfig 1 file changed, 11 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved
diff --git a/src/soc/intel/xeon_sp/cpx/Kconfig b/src/soc/intel/xeon_sp/cpx/Kconfig index 9c6450e..bd1fa97 100644 --- a/src/soc/intel/xeon_sp/cpx/Kconfig +++ b/src/soc/intel/xeon_sp/cpx/Kconfig @@ -68,4 +68,15 @@
select CACHE_MRC_SETTINGS
+# CPX-SP has 2 IMCs, 3 channels per IMC, 2 DIMMs per channel +# Default value is set to one socket, full config. +config DIMM_MAX + int + default 12 + +# DDR4 +config DIMM_SPD_SIZE + int + default 512 + endif
-
Angel Pons (Code Review) -
Jonathan Zhang (Code Review)